Vue Framework

.vscode/launch.json

@@ -1,27 +1,29 @@
 {
     "version": "0.2.0",
     "configurations": [
+        {
+            "type": "chrome",
+            "name": "Launch Chrome Debugger",
+            "request": "launch",
+            "url": "http://localhost:5173/index.html",
+            "webRoot": "${workspaceFolder}/webgui"
+        },
         {
             "type": "firefox",
+            "name": "Launch Firefox Debugger (not recommended, use chrome instead)",
             "request": "launch",
             "reAttach": true,
-            "name": "Launch Vite Firefox Debugger",
             "url": "http://localhost:5173/index.html",
-            "webRoot": "${workspaceFolder}/webgui"
+            "webRoot": "${workspaceFolder}/webgui",
+
         },
         {
-            "name": "Python: Current File",
             "type": "python",
+            "name": "Python: Current File",
             "request": "launch",
             "program": "${file}",
             "console": "integratedTerminal",
             "justMyCode": true
-        },
-        {
-            "type": "chrome",
-            "name": "Launch Chrome Debugger",
-            "request": "launch",
-            "url": "http://127.0.0.1:5173/webgui/index.html"
         }
     ]
 }

architecture_simulator/simulation/riscv_simulation.py

@@ -81,10 +81,13 @@ def run(self):
 
     def load_program(self, program: str):
         """Loads a text form program into the simulation.
+        Resets the state before loading the new program.
 
         Args:
             program (str): A program which complies with (a subset of) the RISC-V syntax.
         """
+        self.state.memory.reset()
+        self.state.instruction_memory.reset()
         parser = RiscvParser()
         parser.parse(program=program, state=self.state)
 
@@ -97,8 +100,16 @@ def has_instructions(self) -> bool:
     def get_performance_metrics(self) -> RiscvPerformanceMetrics:
         return self.state.performance_metrics
 
-    def get_instruction_memory_repr(self) -> list[tuple[str, str, str]]:
-        """Returns a list of the address (in hex), instruction and stage of the instruction for all instructions in the instruction memory.
+    def get_register_entries(self) -> list[tuple[str, str, str, str]]:
+        """Returns the contents of the register file as bin, udec, hex, sdec values.
+
+        Returns:
+            list[tuple[str, str, str, str]]: Register values as tuples of (bin, udec, hex, sdec)
+        """
+        return self.state.register_file.reg_repr()
+
+    def get_instruction_memory_entries(self) -> list[tuple[str, str, str]]:
+        """Returns a list of the address (in hex), instruction and pipeline stage of the instruction for all instructions in the instruction memory.
 
         Returns:
             list[tuple[str, str, str]]: List of (address, instruction, stage).
@@ -112,7 +123,7 @@ def get_instruction_memory_repr(self) -> list[tuple[str, str, str]]:
 
         return [
             (
-                "0x" + "{:x}".format(address),
+                "0x" + "{:03X}".format(address),
                 instruction,
                 pipeline_stages_addresses[address]
                 if address in pipeline_stages_addresses
@@ -121,11 +132,13 @@ def get_instruction_memory_repr(self) -> list[tuple[str, str, str]]:
             for address, instruction in self.state.instruction_memory.get_representation()
         ]
 
-    def get_data_memory_repr(self) -> list[tuple[str, tuple[str, str, str, str]]]:
+    def get_data_memory_entries(
+        self,
+    ) -> list[tuple[tuple[int, str], tuple[str, str, str, str]]]:
         memory_repr = self.state.memory.wordwise_repr()
         result = []
         for key, values in sorted(memory_repr.items()):
-            result.append(("0x" + "{:X}".format(key), values))
+            result.append(((key, "0x" + "{:08X}".format(key)), values))
         return result
 
     def get_riscv_five_stage_svg_update_values(self) -> list[tuple[str, str, Any]]:

architecture_simulator/simulation/simulation.py

@@ -59,4 +59,4 @@ def get_performance_metrics_str(self) -> str:
         Returns:
             str: The string representation of the performance metrics.
         """
-        return str(self.get_performance_metrics)
+        return str(self.get_performance_metrics())

architecture_simulator/simulation/toy_simulation.py

@@ -36,6 +36,7 @@ def __init__(
         self,
         unified_memory_size: Optional[int] = None,
     ):
+        self.unified_memory_size = unified_memory_size
         self.state = ToyArchitecturalState(unified_memory_size)
         self.next_cycle = 1
         super().__init__()
@@ -116,7 +117,7 @@ def run(self):
         self.state.performance_metrics.stop_timer()
 
     def load_program(self, program: str):
-        self.state = ToyArchitecturalState()
+        self.state = ToyArchitecturalState(unified_memory_size=self.unified_memory_size)
         parser = ToyParser()
         parser.parse(program=program, state=self.state)
 
@@ -155,16 +156,16 @@ def get_register_representations(self) -> dict[str, tuple[str, str, str, str]]:
 
     def get_memory_table_entries(
         self,
-    ) -> list[tuple[int, tuple[str, str, str, str], str, str]]:
+    ) -> list[tuple[tuple[int, str], tuple[str, str, str, str], str, str]]:
         """Returns the values to display in the memory table.
 
         Returns:
-            list[tuple[int, tuple[str, str, str, str], str, str]]: Sorted list of (address, representatinos, instruction_representation, current_cycle).
+            list[tuple[tuple[int, str], tuple[str, str, str, str], str, str]]: Sorted list of ((int address, hex address), representations, instruction_representation, current_cycle).
                 instruction_representation will be "-" if the address doesn't count as storing an instruction.
                 current_cycle will be "1", "2" or "".
         """
         entries = self.state.memory.half_wordwise_repr()
-        result: list[tuple[int, tuple[str, str, str, str], str, str]] = []
+        result = []
         current_cycle = "1" if self.next_cycle == 2 else "2"
         # iterate over all entries in the memory
         for address, values in sorted(entries.items()):
@@ -177,9 +178,11 @@ def get_memory_table_entries(
                 self.state.address_of_current_instruction is not None
                 and address == self.state.address_of_current_instruction
             )
+            # make a int and hex address
+            addresses = (address, "0x{:03X}".format(address))
             result.append(
                 (
-                    address,
+                    addresses,
                     values,
                     instruction_representation,
                     current_cycle if is_current_instruction else "",

architecture_simulator/uarch/instruction_memory.py

@@ -26,6 +26,10 @@ class InstructionMemory(Generic[T]):
         )
     )
 
+    def reset(self):
+        """Clears the instruction memory."""
+        self.instructions = {}
+
     def get_representation(self) -> list[tuple[int, str]]:
         """Returns a list of string representations for all instructions and their address. Sorted by address.
 

architecture_simulator/uarch/memory.py

@@ -69,6 +69,10 @@ def __init__(
         )
         self.memory_file: dict[int, T] = dict()
 
+    def reset(self):
+        """Clears the memory."""
+        self.memory_file = {}
+
     def assert_address_in_range(self, address: int):
         """
         Asserts that the given address is within the valid memory address range. Raises MemoryAddressError if the address is outside the allowed range.

architecture_simulator/uarch/riscv/register_file.py

@@ -34,18 +34,13 @@ class RegisterFile:
         default_factory=lambda: Registers([fixedint.MutableUInt32(0)] * 32)
     )
 
-    def reg_repr(self) -> dict[int, tuple[str, str, str, str]]:
-        """Returns the contents of the register file as binary, unsigned decimal, hexadecimal, signed decimal values.
+    def reg_repr(self) -> list[tuple[str, str, str, str]]:
+        """Returns the contents of the register file as bin, udec, hex, sdec values.
 
         Returns:
-            dict[int, tuple[str, str, str, str]]: keys: register indices. Values: Register values as tuple of (binary, unsigned decimal, hexadecimal, signed decimal)
+            list[tuple[str, str, str, str]]: Register values as tuples of (bin, udec, hex, sdec)
         """
-        reg_repr: dict[int, tuple[str, str, str, str]] = dict()
-        index = 0
-        for reg in self.registers:
-            reg_repr[index] = get_32_bit_representations(int(reg))
-            index += 1
-        return reg_repr
+        return [get_32_bit_representations(int(reg)) for reg in self.registers]
 
     def get_abi_names(self, register: int) -> str:
         """Get the ABI name for the given register index.

jsconfig.json

@@ -0,0 +1,8 @@
+{
+  "compilerOptions": {
+    "paths": {
+      "@/*": ["./webgui/src/*"]
+    }
+  },
+  "exclude": ["node_modules", "dist"]
+}