Merge pull request #3714 from elagil/stm32h5_ucpd_example

Fix/clean up STM32H5 UCPD example

embassy-stm32/Cargo.toml

@@ -73,7 +73,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d87131cfec93a6dbd21422ac36d43ce9562aab7f" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-567fd0b1b7dfd9c1aa9e54d365547afe1ceb1241" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d87131cfec93a6dbd21422ac36d43ce9562aab7f", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-567fd0b1b7dfd9c1aa9e54d365547afe1ceb1241", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]

embassy-stm32/src/adc/g4.rs

@@ -178,14 +178,14 @@ impl<'d, T: Instance> Adc<'d, T> {
     fn configure_differential_inputs(&mut self) {
         T::regs().difsel().modify(|w| {
             for n in 0..18 {
-                w.set_difsel(n, Difsel::SINGLEENDED);
+                w.set_difsel(n, Difsel::SINGLE_ENDED);
             }
         });
     }
 
     fn calibrate(&mut self) {
         T::regs().cr().modify(|w| {
-            w.set_adcaldif(Adcaldif::SINGLEENDED);
+            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
         });
 
         T::regs().cr().modify(|w| w.set_adcal(true));
@@ -266,7 +266,7 @@ impl<'d, T: Instance> Adc<'d, T> {
                 if enable {
                     Difsel::DIFFERENTIAL
                 } else {
-                    Difsel::SINGLEENDED
+                    Difsel::SINGLE_ENDED
                 },
             );
         });
@@ -435,7 +435,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr().modify(|reg| {
             reg.set_discen(false);
             reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONESHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
             reg.set_dmaen(Dmaen::ENABLE);
         });
 

embassy-stm32/src/adc/ringbuffered_v2.rs

@@ -312,7 +312,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
             // DMA requests are issues as long as DMA=1 and data are converted.
             w.set_dds(vals::Dds::CONTINUOUS);
             // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACHCONVERSION);
+            w.set_eocs(vals::Eocs::EACH_CONVERSION);
         });
 
         // Begin ADC conversions

embassy-stm32/src/adc/u5_adc4.rs

@@ -416,7 +416,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
 
         T::regs().cfgr1().modify(|reg| {
             reg.set_dmaen(true);
-            reg.set_dmacfg(Adc4Dmacfg::ONESHOT);
+            reg.set_dmacfg(Adc4Dmacfg::ONE_SHOT);
             reg.set_chselrmod(false);
         });
 

embassy-stm32/src/adc/v1.rs

@@ -160,7 +160,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         channel.setup();
 
         // A.7.5 Single conversion sequence code example - Software trigger
-        T::regs().chselr().write(|reg| reg.set_chselx(ch_num as usize, true));
+        T::regs().chselr().write(|reg| reg.set_chsel_x(ch_num as usize, true));
 
         self.convert().await
     }

embassy-stm32/src/adc/v3.rs

@@ -366,14 +366,14 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr().modify(|reg| {
             reg.set_discen(false);
             reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONESHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
             reg.set_dmaen(true);
         });
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
             reg.set_discen(false);
             reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONESHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
             reg.set_dmaen(true);
         });
 

embassy-stm32/src/adc/v4.rs

@@ -214,15 +214,15 @@ impl<'d, T: Instance> Adc<'d, T> {
     fn configure_differential_inputs(&mut self) {
         T::regs().difsel().modify(|w| {
             for n in 0..20 {
-                w.set_difsel(n, Difsel::SINGLEENDED);
+                w.set_difsel(n, Difsel::SINGLE_ENDED);
             }
         });
     }
 
     fn calibrate(&mut self) {
         T::regs().cr().modify(|w| {
             #[cfg(not(adc_u5))]
-            w.set_adcaldif(Adcaldif::SINGLEENDED);
+            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
             w.set_adcallin(true);
         });
 
@@ -420,7 +420,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
         T::regs().cfgr().modify(|reg| {
             reg.set_cont(true);
-            reg.set_dmngt(Dmngt::DMA_ONESHOT);
+            reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
         });
 
         let request = rx_dma.request();

embassy-stm32/src/can/bxcan/registers.rs

@@ -166,16 +166,16 @@ impl Registers {
             return Some(BusError::BusPassive);
         } else if err.ewgf() {
             return Some(BusError::BusWarning);
-        } else if err.lec() != Lec::NOERROR {
+        } else if err.lec() != Lec::NO_ERROR {
             return Some(match err.lec() {
                 Lec::STUFF => BusError::Stuff,
                 Lec::FORM => BusError::Form,
                 Lec::ACK => BusError::Acknowledge,
-                Lec::BITRECESSIVE => BusError::BitRecessive,
-                Lec::BITDOMINANT => BusError::BitDominant,
+                Lec::BIT_RECESSIVE => BusError::BitRecessive,
+                Lec::BIT_DOMINANT => BusError::BitDominant,
                 Lec::CRC => BusError::Crc,
                 Lec::CUSTOM => BusError::Software,
-                Lec::NOERROR => unreachable!(),
+                Lec::NO_ERROR => unreachable!(),
             });
         }
         None

embassy-stm32/src/crc/v2v3.rs

@@ -118,7 +118,7 @@ impl<'d> Crc<'d> {
             w.set_rev_in(match self._config.reverse_in {
                 InputReverseConfig::None => vals::RevIn::NORMAL,
                 InputReverseConfig::Byte => vals::RevIn::BYTE,
-                InputReverseConfig::Halfword => vals::RevIn::HALFWORD,
+                InputReverseConfig::Halfword => vals::RevIn::HALF_WORD,
                 InputReverseConfig::Word => vals::RevIn::WORD,
             });
             // configure the polynomial.

embassy-stm32/src/dma/dma_bdma.rs

@@ -100,7 +100,7 @@ impl From<Priority> for pac::dma::vals::Pl {
             Priority::Low => pac::dma::vals::Pl::LOW,
             Priority::Medium => pac::dma::vals::Pl::MEDIUM,
             Priority::High => pac::dma::vals::Pl::HIGH,
-            Priority::VeryHigh => pac::dma::vals::Pl::VERYHIGH,
+            Priority::VeryHigh => pac::dma::vals::Pl::VERY_HIGH,
         }
     }
 }
@@ -112,7 +112,7 @@ impl From<Priority> for pac::bdma::vals::Pl {
             Priority::Low => pac::bdma::vals::Pl::LOW,
             Priority::Medium => pac::bdma::vals::Pl::MEDIUM,
             Priority::High => pac::bdma::vals::Pl::HIGH,
-            Priority::VeryHigh => pac::bdma::vals::Pl::VERYHIGH,
+            Priority::VeryHigh => pac::bdma::vals::Pl::VERY_HIGH,
         }
     }
 }
@@ -138,8 +138,8 @@ mod dma_only {
     impl From<Dir> for vals::Dir {
         fn from(raw: Dir) -> Self {
             match raw {
-                Dir::MemoryToPeripheral => Self::MEMORYTOPERIPHERAL,
-                Dir::PeripheralToMemory => Self::PERIPHERALTOMEMORY,
+                Dir::MemoryToPeripheral => Self::MEMORY_TO_PERIPHERAL,
+                Dir::PeripheralToMemory => Self::PERIPHERAL_TO_MEMORY,
             }
         }
     }
@@ -207,7 +207,7 @@ mod dma_only {
             match value {
                 FifoThreshold::Quarter => vals::Fth::QUARTER,
                 FifoThreshold::Half => vals::Fth::HALF,
-                FifoThreshold::ThreeQuarters => vals::Fth::THREEQUARTERS,
+                FifoThreshold::ThreeQuarters => vals::Fth::THREE_QUARTERS,
                 FifoThreshold::Full => vals::Fth::FULL,
             }
         }
@@ -233,8 +233,8 @@ mod bdma_only {
     impl From<Dir> for vals::Dir {
         fn from(raw: Dir) -> Self {
             match raw {
-                Dir::MemoryToPeripheral => Self::FROMMEMORY,
-                Dir::PeripheralToMemory => Self::FROMPERIPHERAL,
+                Dir::MemoryToPeripheral => Self::FROM_MEMORY,
+                Dir::PeripheralToMemory => Self::FROM_PERIPHERAL,
             }
         }
     }

embassy-stm32/src/dma/gpdma.rs

@@ -38,7 +38,7 @@ impl From<WordSize> for vals::Dw {
     fn from(raw: WordSize) -> Self {
         match raw {
             WordSize::OneByte => Self::BYTE,
-            WordSize::TwoBytes => Self::HALFWORD,
+            WordSize::TwoBytes => Self::HALF_WORD,
             WordSize::FourBytes => Self::WORD,
         }
     }
@@ -240,8 +240,8 @@ impl<'a> Transfer<'a> {
         });
         ch.tr2().write(|w| {
             w.set_dreq(match dir {
-                Dir::MemoryToPeripheral => vals::Dreq::DESTINATIONPERIPHERAL,
-                Dir::PeripheralToMemory => vals::Dreq::SOURCEPERIPHERAL,
+                Dir::MemoryToPeripheral => vals::Dreq::DESTINATION_PERIPHERAL,
+                Dir::PeripheralToMemory => vals::Dreq::SOURCE_PERIPHERAL,
             });
             w.set_reqsel(request);
         });

embassy-stm32/src/eth/v1/mod.rs

@@ -159,8 +159,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
             w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times
             w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
             w.set_fes(Fes::FES100); // fast ethernet speed
-            w.set_dm(Dm::FULLDUPLEX); // full duplex
-                                      // TODO: Carrier sense ? ECRSFD
+            w.set_dm(Dm::FULL_DUPLEX); // full duplex
+                                       // TODO: Carrier sense ? ECRSFD
         });
 
         // Set the mac to pass all multicast packets
@@ -186,8 +186,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
 
         // Transfer and Forward, Receive and Forward
         dma.dmaomr().modify(|w| {
-            w.set_tsf(Tsf::STOREFORWARD);
-            w.set_rsf(Rsf::STOREFORWARD);
+            w.set_tsf(Tsf::STORE_FORWARD);
+            w.set_rsf(Rsf::STORE_FORWARD);
         });
 
         dma.dmabmr().modify(|w| {

embassy-stm32/src/eth/v1/rx_desc.rs

@@ -168,15 +168,15 @@ impl<'a> RDesRing<'a> {
             //  Reset or Stop Receive Command issued
             Rps::STOPPED => RunningState::Stopped,
             //  Fetching receive transfer descriptor
-            Rps::RUNNINGFETCHING => RunningState::Running,
+            Rps::RUNNING_FETCHING => RunningState::Running,
             //  Waiting for receive packet
-            Rps::RUNNINGWAITING => RunningState::Running,
+            Rps::RUNNING_WAITING => RunningState::Running,
             //  Receive descriptor unavailable
             Rps::SUSPENDED => RunningState::Stopped,
             //  Closing receive descriptor
             Rps::_RESERVED_5 => RunningState::Running,
             //  Transferring the receive packet data from receive buffer to host memory
-            Rps::RUNNINGWRITING => RunningState::Running,
+            Rps::RUNNING_WRITING => RunningState::Running,
             _ => RunningState::Unknown,
         }
     }

embassy-stm32/src/flash/f4.rs

@@ -469,7 +469,7 @@ fn pa12_is_output_pull_low() -> bool {
     use pac::GPIOA;
     const PIN: usize = 12;
     GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT
-        && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULLDOWN
+        && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULL_DOWN
         && GPIOA.odr().read().odr(PIN) == vals::Odr::LOW
 }
 

embassy-stm32/src/gpio.rs

@@ -61,7 +61,7 @@ impl<'d> Flex<'d> {
             #[cfg(gpio_v2)]
             {
                 r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr()));
-                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
+                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSH_PULL));
                 r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
             }
         });
@@ -82,13 +82,13 @@ impl<'d> Flex<'d> {
             {
                 r.cr(n / 8).modify(|w| {
                     w.set_mode(n % 8, speed.to_mode());
-                    w.set_cnf_out(n % 8, vals::CnfOut::PUSHPULL);
+                    w.set_cnf_out(n % 8, vals::CnfOut::PUSH_PULL);
                 });
             }
             #[cfg(gpio_v2)]
             {
                 r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
-                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
+                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSH_PULL));
                 r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
                 r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
             }
@@ -112,7 +112,7 @@ impl<'d> Flex<'d> {
             let r = self.pin.block();
             let n = self.pin.pin() as usize;
             r.cr(n / 8).modify(|w| w.set_mode(n % 8, speed.to_mode()));
-            r.cr(n / 8).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPENDRAIN));
+            r.cr(n / 8).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPEN_DRAIN));
         });
 
         #[cfg(gpio_v2)]
@@ -130,7 +130,7 @@ impl<'d> Flex<'d> {
             let r = self.pin.block();
             let n = self.pin.pin() as usize;
             r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr()));
-            r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPENDRAIN));
+            r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPEN_DRAIN));
             r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
             r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
         });
@@ -253,8 +253,8 @@ impl Pull {
     const fn to_pupdr(self) -> vals::Pupdr {
         match self {
             Pull::None => vals::Pupdr::FLOATING,
-            Pull::Up => vals::Pupdr::PULLUP,
-            Pull::Down => vals::Pupdr::PULLDOWN,
+            Pull::Up => vals::Pupdr::PULL_UP,
+            Pull::Down => vals::Pupdr::PULL_DOWN,
         }
     }
 }
@@ -293,11 +293,11 @@ impl Speed {
     #[cfg(gpio_v2)]
     const fn to_ospeedr(self: Speed) -> vals::Ospeedr {
         match self {
-            Speed::Low => vals::Ospeedr::LOWSPEED,
-            Speed::Medium => vals::Ospeedr::MEDIUMSPEED,
+            Speed::Low => vals::Ospeedr::LOW_SPEED,
+            Speed::Medium => vals::Ospeedr::MEDIUM_SPEED,
             #[cfg(not(syscfg_f0))]
-            Speed::High => vals::Ospeedr::HIGHSPEED,
-            Speed::VeryHigh => vals::Ospeedr::VERYHIGHSPEED,
+            Speed::High => vals::Ospeedr::HIGH_SPEED,
+            Speed::VeryHigh => vals::Ospeedr::VERY_HIGH_SPEED,
         }
     }
 }
@@ -539,16 +539,16 @@ impl OutputType {
     #[cfg(gpio_v1)]
     const fn to_cnf_out(self) -> vals::CnfOut {
         match self {
-            OutputType::PushPull => vals::CnfOut::ALTPUSHPULL,
-            OutputType::OpenDrain => vals::CnfOut::ALTOPENDRAIN,
+            OutputType::PushPull => vals::CnfOut::ALT_PUSH_PULL,
+            OutputType::OpenDrain => vals::CnfOut::ALT_OPEN_DRAIN,
         }
     }
 
     #[cfg(gpio_v2)]
     const fn to_ot(self) -> vals::Ot {
         match self {
-            OutputType::PushPull => vals::Ot::PUSHPULL,
-            OutputType::OpenDrain => vals::Ot::OPENDRAIN,
+            OutputType::PushPull => vals::Ot::PUSH_PULL,
+            OutputType::OpenDrain => vals::Ot::OPEN_DRAIN,
         }
     }
 }
@@ -624,8 +624,8 @@ impl AfType {
     pub const fn input(pull: Pull) -> Self {
         Self {
             pupdr: pull.to_pupdr(),
-            ot: vals::Ot::PUSHPULL,
-            ospeedr: vals::Ospeedr::LOWSPEED,
+            ot: vals::Ot::PUSH_PULL,
+            ospeedr: vals::Ospeedr::LOW_SPEED,
         }
     }
 
@@ -705,8 +705,8 @@ fn get_pull(pin_port: u8) -> Pull {
     #[cfg(gpio_v2)]
     return match r.pupdr().read().pupdr(n) {
         vals::Pupdr::FLOATING => Pull::None,
-        vals::Pupdr::PULLDOWN => Pull::Down,
-        vals::Pupdr::PULLUP => Pull::Up,
+        vals::Pupdr::PULL_DOWN => Pull::Down,
+        vals::Pupdr::PULL_UP => Pull::Up,
         vals::Pupdr::_RESERVED_3 => Pull::None,
     };
 }