Merge pull request #135 from openchips/pcie-gen4

phy/usppciephy: Use double wide axis for gen4
enjoy-digital · May 2, 2024 · 9809d75 · 9809d75
2 parents 5b45dbf + c8e76e1
commit 9809d75
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Showing 3 changed files with 13 additions and 5 deletions.
diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py
@@ -3,6 +3,7 @@
 #
 # Copyright (c) 2020-2023 Enjoy-Digital <enjoy-digital.fr>
 # Copyright (c) 2022 Sylvain Munaut <tnt@246tNt.com>
+# Copyright (c) 2024 John Simons <jammsimons@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
@@ -415,10 +416,14 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
 
         verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_usp")
         platform.add_source(os.path.join(verilog_path, "axis_iff.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_x{self.nlanes}.v"))
+
+        nvlanes = {"gen3": self.nlanes, "gen4": self.nlanes*2}[self.speed]
+
+        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_x{nvlanes}.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_x{nvlanes}.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_x{nvlanes}.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_x{nvlanes}.v"))
+
         platform.add_source(os.path.join(verilog_path, "pcie_usp_support.v"))
 
     # External Hard IP -----------------------------------------------------------------------------

diff --git a/litepcie/software/kernel/liteuart.c b/litepcie/software/kernel/liteuart.c
@@ -3,6 +3,7 @@
  * LiteUART serial controller (LiteX) Driver
  *
  * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
+ * Copyright (C) 2024 John Simons <jammsimons@gmail.com>
  */
 
 #include <linux/console.h>
@@ -11,6 +12,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/slab.h>

diff --git a/litepcie/tlp/packetizer.py b/litepcie/tlp/packetizer.py
@@ -2,6 +2,7 @@
 # This file is part of LitePCIe.
 #
 # Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2024 John Simons <jammsimons@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
@@ -804,7 +805,7 @@ def __init__(self, data_width, endianness, address_width=32, capabilities=["REQU
 
             # On Ultrascale(+) / 256-bit, force to 64-bit (for 4DWs format).
             try:
-                force_64b = (LiteXContext.platform.device[:4] in ["xcku", "xcvu", "xczu"]) and (data_width in [256])
+                force_64b = (LiteXContext.platform.device[:4] in ["xcku", "xcvu", "xczu", 'xcau']) and (data_width in [256])
             except:
                 force_64b = False