Add Configuration and PTM TLP support.

litepcie/common.py

@@ -38,6 +38,25 @@ def phy_layout(data_width):
     ]
     return EndpointDescription(layout)
 
+def configuration_layout(data_width, address_width=32):
+    layout = [
+        # Request Parameters.
+        ("req_id",          16), # Requester ID.
+        ("we",               1), # Configuration type; 0 : Read / 1 : Write.
+        ("bus_number",       8), # Configuration Bus number.
+        ("device_no",        5), # Configuration Device number.
+        ("func",             3), # Configuration Function number.
+        ("ext_reg",          3), # Configuration Extended Register.
+        ("register_no",      6), # Configuration Register number.
+
+        # Data Stream.
+        ("dat", data_width),
+
+        # Internal LitePCIe Routing/Identification.
+        ("channel", 8), # Crossbar's channel (Used for internal routing).
+    ]
+    return EndpointDescription(layout)
+
 def request_layout(data_width, address_width=32):
     layout = [
         # Request Parameters.
@@ -76,6 +95,23 @@ def completion_layout(data_width, address_width=32):
     ]
     return EndpointDescription(layout)
 
+def ptm_layout(data_width):
+    layout = [
+        ("request",       1), # Request.
+        ("response",      1), # Response.
+        ("requester_id", 16), # Requester ID.
+        ("length",       16), # Length.
+        ("message_code", 16), # Message Code.
+
+        # Data Stream.
+        ("dat", data_width),
+
+        # Internal LitePCIe Routing/Identification.
+        ("channel", 8), # Crossbar's channel (Used for internal routing).
+    ]
+    return EndpointDescription(layout)
+
+
 def msi_layout():
     return [("dat", 8)]
 

litepcie/core/endpoint.py

@@ -1,11 +1,13 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.interconnect.csr import *
 
 from litepcie.tlp.depacketizer import LitePCIeTLPDepacketizer
@@ -14,20 +16,32 @@
 
 # LitePCIe Endpoint --------------------------------------------------------------------------------
 
-class LitePCIeEndpoint(Module):
-    def __init__(self, phy, max_pending_requests=4, address_width=32, endianness="big", cmp_bufs_buffered=True):
+class LitePCIeEndpoint(LiteXModule):
+    def __init__(self, phy, max_pending_requests=4, address_width=32, endianness="big",
+        cmp_bufs_buffered = True,
+        with_ptm          = False,
+    ):
         self.phy                  = phy
         self.max_pending_requests = max_pending_requests
 
         # # #
 
         # TLP Packetizer / Depacketizer ------------------------------------------------------------
+
         if hasattr(phy, "sink") and hasattr(phy, "source"):
             # Shared Request/Completion channels
-            depacketizer = LitePCIeTLPDepacketizer(phy.data_width, endianness, phy.bar0_mask)
-            packetizer   = LitePCIeTLPPacketizer(phy.data_width, endianness, address_width)
-            self.submodules.depacketizer = depacketizer
-            self.submodules.packetizer   = packetizer
+            self.depacketizer = depacketizer = LitePCIeTLPDepacketizer(
+                data_width   = phy.data_width,
+                endianness   = endianness,
+                address_mask = phy.bar0_mask,
+                capabilities = ["REQUEST", "COMPLETION"] + (["PTM"] if with_ptm else []),
+            )
+            self.packetizer = packetizer = LitePCIeTLPPacketizer(
+                data_width    = phy.data_width,
+                endianness    = endianness,
+                address_width = address_width,
+                capabilities  = ["REQUEST", "COMPLETION"] + (["PTM"] if with_ptm else []),
+            )
             self.comb += [
                 phy.source.connect(depacketizer.sink),
                 packetizer.source.connect(phy.sink)
@@ -38,14 +52,30 @@ def __init__(self, phy, max_pending_requests=4, address_width=32, endianness="bi
             cmp_source = depacketizer.cmp_source
         else:
             # Separate Request/Completion channels
-            cmp_depacketizer = LitePCIeTLPDepacketizer(phy.data_width, endianness, phy.bar0_mask)
-            req_depacketizer = LitePCIeTLPDepacketizer(phy.data_width, endianness, phy.bar0_mask)
-            cmp_packetizer   = LitePCIeTLPPacketizer(phy.data_width, endianness, address_width)
-            req_packetizer   = LitePCIeTLPPacketizer(phy.data_width, endianness, address_width)
-            self.submodules.cmp_depacketizer = cmp_depacketizer
-            self.submodules.req_depacketizer = req_depacketizer
-            self.submodules.cmp_packetizer   = cmp_packetizer
-            self.submodules.req_packetizer   = req_packetizer
+            self.cmp_depacketizer = cmp_depacketizer = LitePCIeTLPDepacketizer(
+                data_width   = phy.data_width,
+                endianness   = endianness,
+                address_mask = phy.bar0_mask,
+                capabilities = ["COMPLETION"] + (["PTM"] if with_ptm else []),
+            )
+            self.req_depacketizer = req_depacketizer = LitePCIeTLPDepacketizer(
+                data_width   = phy.data_width,
+                endianness   = endianness,
+                address_mask = phy.bar0_mask,
+                capabilities = ["REQUEST"] + (["PTM"] if with_ptm else []),
+            )
+            self.cmp_packetizer = cmp_packetizer = LitePCIeTLPPacketizer(
+                data_width    = phy.data_width,
+                endianness    = endianness,
+                address_width = address_width,
+                capabilities  = ["COMPLETION"] + (["PTM"] if with_ptm else []),
+            )
+            self.req_packetizer = req_packetizer = LitePCIeTLPPacketizer(
+                data_width    = phy.data_width,
+                endianness    = endianness,
+                address_width = address_width,
+                capabilities  = ["REQUEST"] + (["PTM"] if with_ptm else []),
+            )
             self.comb += [
                 phy.cmp_source.connect(cmp_depacketizer.sink),
                 phy.req_source.connect(req_depacketizer.sink),
@@ -58,21 +88,23 @@ def __init__(self, phy, max_pending_requests=4, address_width=32, endianness="bi
             cmp_source = cmp_depacketizer.cmp_source
 
         # Crossbar ---------------------------------------------------------------------------------
-        crossbar = LitePCIeCrossbar(
+
+        self.crossbar = crossbar = LitePCIeCrossbar(
             data_width           = phy.data_width,
             address_width        = address_width,
             max_pending_requests = max_pending_requests,
-            cmp_bufs_buffered    = cmp_bufs_buffered
+            cmp_bufs_buffered    = cmp_bufs_buffered,
         )
-        self.submodules.crossbar = crossbar
 
         # Slave: HOST initiates the transactions ---------------------------------------------------
+
         self.comb += [
             req_source.connect(crossbar.phy_slave.sink),
             crossbar.phy_slave.source.connect(cmp_sink),
         ]
 
         # Master: FPGA initiates the transactions --------------------------------------------------
+
         self.comb += [
             crossbar.phy_master.source.connect(req_sink),
             cmp_source.connect(crossbar.phy_master.sink),