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bench/sim: Update.
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enjoy-digital committed Sep 2, 2024
1 parent b243b3b commit fefee15
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions bench/sim.py
Original file line number Diff line number Diff line change
Expand Up @@ -34,11 +34,11 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
# Sampler --------------------------------------------------------------------------------
data = Signal(8)
self.sync += data.eq(data + 1)
self.submodules.sampler = Sampler(data)
self.sampler = Sampler(data)

# DRAMFIFO ---------------------------------------------------------------------------------
from litedram.frontend.fifo import LiteDRAMFIFO
self.submodules.fifo = LiteDRAMFIFO(
self.fifo = LiteDRAMFIFO(
data_width = 8,
base = 0x00000000,
depth = 0x01000000, # 16MB
Expand All @@ -49,7 +49,7 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
# UDPStreamer ------------------------------------------------------------------------------
from liteeth.common import convert_ip
from liteeth.frontend.stream import LiteEthStream2UDPTX
udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
udp_port = self.ethcore_etherbone.udp.crossbar.get_port(host_udp_port, dw=8)
udp_streamer = LiteEthStream2UDPTX(
ip_address = convert_ip(host_ip),
udp_port = host_udp_port,
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