Merge pull request #2143 from FlyGoat/csr-bridge-width

soc/integration/soc: Fix CSRBridge Bus Width conversion
enjoy-digital · Dec 18, 2024 · 1b47407 · 1b47407
2 parents d05b661 + c52a2ca
commit 1b47407
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Showing 4 changed files with 9 additions and 4 deletions.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1138,13 +1138,14 @@ def add_csr_bridge(self, name="csr", origin=None, register=False):
         }[self.bus.standard]
         csr_bridge_name = f"{name}_bridge"
         self.check_if_exists(csr_bridge_name)
+        data_width = self.csr.data_width
         csr_bridge = csr_bridge_cls(
             bus_bridge_cls(
                 address_width = self.bus.address_width,
-                data_width    = self.bus.data_width),
+                data_width    = data_width),
             bus_csr = csr_bus.Interface(
                 address_width = self.csr.address_width,
-                data_width    = self.csr.data_width),
+                data_width    = data_width),
             register = register)
         self.logger.info("CSR Bridge {} {}.".format(
             colorer(name, color="underline"),

diff --git a/litex/soc/interconnect/axi/axi_lite_to_csr.py b/litex/soc/interconnect/axi/axi_lite_to_csr.py
@@ -29,6 +29,8 @@ def __init__(self, axi_lite=None, bus_csr=None, register=False):
         self.axi_lite = axi_lite
         self.csr      = bus_csr
 
+        assert axi_lite.data_width == bus_csr.data_width
+
         fsm, comb = axi_lite_to_simple(
             axi_lite   = self.axi_lite,
             port_adr   = self.csr.adr,

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
@@ -588,6 +588,8 @@ def __init__(self, bus_wishbone=None, bus_csr=None, register=True):
             # If no Wishbone bus provided, create it with default parameters.
             self.wishbone = Interface()
 
+        assert self.wishbone.data_width == self.csr.data_width
+
         # # #
 
         wishbone_adr_shift = {

diff --git a/test/test_axi_lite.py b/test/test_axi_lite.py
@@ -258,8 +258,8 @@ def csr_mem_handler(csr, mem):
 
         class DUT(Module):
             def __init__(self):
-                self.axi_lite = AXILiteInterface()
-                self.csr = csr_bus.Interface()
+                self.axi_lite = AXILiteInterface(data_width=32)
+                self.csr = csr_bus.Interface(data_width=32)
                 self.submodules.axilite2csr = AXILite2CSR(self.axi_lite, self.csr)
                 self.errors = 0