Initial commit

README.md

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+# Super Breakout for Analogue Pocket
+
++ FPGA implementation by james10952001 of Arcade _Dominos_ (Atari, 1977) for Analogue Pocket.
++ Ported from [MiSTer.](https://github.com/MiSTer-devel/Arcade-Dominos_MiSTer/)
++ Multiplayer support via dock.
+
+## ROM Instructions
+
+ROM files are not included, you must use [mra-tools-c](https://github.com/sebdel/mra-tools-c/) to convert to a singular `dominos.rom` file, then place the ROM file in `/Assets/dominos/common`.

dist/Cores/ericlewis.Dominos/audio.json

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+{
+  "audio": {
+    "magic": "APF_VER_1" 
+  }
+}

dist/Cores/ericlewis.Dominos/core.json

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+{
+    "core": {
+        "magic": "APF_VER_1",
+        "metadata": {
+            "platform_ids": ["dominos"],
+            "shortname": "Dominos",
+            "description": "Atari's 1977 Dominos.",
+            "author": "ericlewis",
+            "url": "https://github.com/ericlewis/openfpga-dominos",
+            "version": "0.0.1",
+            "date_release": "2022-09-16"
+        },
+        "framework": {
+            "target_product": "Analogue Pocket",
+            "version_required": "1.1",
+            "sleep_supported": false,
+            "dock": {
+                "supported": true,
+                "analog_output": false
+            },
+            "hardware": {
+                "link_port": false,
+                "cartridge_adapter": -1
+            }
+        },
+        "cores": [
+            {
+                "name": "default",
+                "id": 0,
+                "filename": "bitstream.rbf_r"
+            }
+        ]
+    }
+}

dist/Cores/ericlewis.Dominos/data.json

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+{
+    "data": {
+        "magic": "APF_VER_1",
+        "data_slots": [
+            {
+                "name": "ROM",
+                "required": true,
+                "parameters": 8,
+                "filename": "dominos.rom",
+                "address": "0x00000000"
+            }
+        ]
+    }
+}

dist/Cores/ericlewis.Dominos/info.txt

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+Atari's Arcade 1977 Dominos. Ported from MiSTer.

dist/Cores/ericlewis.Dominos/input.json

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+{
+    "input": {
+        "magic": "APF_VER_1",
+        "controllers": [
+            {
+                "type": "default",
+                "mappings": [
+                  {
+                    "id": 1,
+                    "name": "Insert Coin",
+                    "key": "pad_btn_select"
+                  },
+                  {
+                    "id": 2,
+                    "name": "Start",
+                    "key": "pad_btn_start"
+                  }
+                ]
+            }
+        ]
+    }
+}

dist/Cores/ericlewis.Dominos/interact.json

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+{
+    "interact": {
+        "magic": "APF_VER_1",
+        "variables": [],
+        "messages": []
+    }
+}

dist/Cores/ericlewis.Dominos/variants.json

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+{
+    "variants": {
+        "magic": "APF_VER_1",
+        "variant_list": []
+    }
+}

dist/Cores/ericlewis.Dominos/video.json

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+{
+    "video": {
+        "magic": "APF_VER_1",
+        "scaler_modes": [
+            {
+                "width": 320,
+                "height": 240,
+                "aspect_w": 4,
+                "aspect_h": 3,
+                "rotation": 0,
+                "mirror": 0
+            }
+        ]
+    }
+}

dist/Platforms/dominos.json

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+{
+  "platform": {
+    "category": "Arcade",
+    "name": "Dominos",
+    "year": 1977,
+    "manufacturer": "Atari"
+  }
+}

mra/Dominos.mra

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+<misterromdescription>
+	<name>Dominos</name>
+	<region></region>
+	<homebrew>no</homebrew>
+	<bootleg>no</bootleg>
+	<version></version>
+	<alternative></alternative>
+	<platform></platform>
+	<series></series>
+	<year>1977</year>
+	<manufacturer>Atari</manufacturer>
+	<category>Maze</category>
+
+	<setname>dominos</setname>
+	<parent>dominos</parent>
+	<mameversion>0220</mameversion>
+	<rbf>dominos</rbf>
+	<about></about>
+
+	<resolution>15kHz</resolution>
+	<rotation>horizontal</rotation>
+	<flip></flip>
+
+	<players>2 (simultaneous)</players>
+	<joystick>4-way</joystick>
+	<special_controls></special_controls>
+	<num_buttons>0</num_buttons>
+	<button_names></button_names>
+
+	<switches></switches>
+
+	<rom index="1"></rom>
+	<rom index="0" md5="3573ac6efbd7ef650d8f53542538e074" zip="dominos.zip">
+		<part crc="738b4413" name="7352-02.d1"></part>
+		<part crc="c84e54e2" name="7438-02.e1"></part>
+		<part crc="4f42fdd6" name="7439-01.p4"></part>
+		<part crc="957dd8df" name="7440-01.r4"></part>
+		<part crc="b8094b4c" name="6400-01.m2"></part>
+		<part crc="857df8db" name="6401-01.e2"></part>
+		</rom>
+	<rom index="2"></rom>
+	<rom index="3"></rom>
+	<rom index="4"></rom>
+
+	<nvram></nvram>
+
+	<remark></remark>
+
+	<mratimestamp>20210430005030</mratimestamp>
+</misterromdescription>

src/fpga/.gitignore

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+*/db/
+*/incremental_db/
+*/simulation/
+*/greybox_tmp/
+incremental_db/
+db/
+PLLJ_PLLSPE_INFO.txt
+c5_pin_model_dump.txt
+cr_ie_info.json
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+*.sof
+*.sopc_builder
+*.summary
+*.txt
+*.bak
+*.cmp
+*.done
+*.xml
+*.sld
+*.cdf
+

src/fpga/ap_core.out.sdc

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+## Generated SDC file "ap_core.out.sdc"
+
+## Copyright (C) 2022  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and any partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel FPGA IP License Agreement, or other applicable license
+## agreement, including, without limitation, that your use is for
+## the sole purpose of programming logic devices manufactured by
+## Intel and sold by Intel or its authorized distributors.  Please
+## refer to the applicable agreement for further details, at
+## https://fpgasoftware.intel.com/eula.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition"
+
+## DATE    "Tue Sep 13 13:20:17 2022"
+
+##
+## DEVICE  "5CEBA4F23C8"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {clk_74a} -period 13.468 -waveform { 0.000 6.734 } [get_ports {clk_74a}]
+create_clock -name {clk_74b} -period 13.468 -waveform { 0.000 6.734 } [get_ports {clk_74b}]
+create_clock -name {bridge_spiclk} -period 13.468 -waveform { 0.000 6.734 } [get_ports {bridge_spiclk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+create_generated_clock -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 48 -divide_by 11 -master_clock {clk_74a} [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 
+create_generated_clock -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 27 -master_clock {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+create_generated_clock -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 27 -phase 7499880/83333 -master_clock {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160  
+set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160  
+set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160  
+set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160  
+set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -setup 0.280  
+set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -hold 0.270  
+set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -setup 0.280  
+set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -hold 0.270  
+set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -setup 0.280  
+set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -hold 0.270  
+set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -setup 0.280  
+set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -hold 0.270  
+set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -hold 0.060  
+set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -setup 0.100  
+set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -hold 0.060  
+set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -setup 0.100  
+set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -hold 0.060  
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks { bridge_spiclk }] -group [get_clocks { clk_74a }] -group [get_clocks { clk_74b }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk }] 
+set_clock_groups -asynchronous -group [get_clocks { bridge_spiclk }] -group [get_clocks { clk_74a }] -group [get_clocks { clk_74b }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk }] 
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

src/fpga/ap_core.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 21:31:36  January 22, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "21:31:36  January 22, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "ap_core"