update module name to match wokwi

info.yaml

@@ -11,7 +11,7 @@ project:
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_ericsmi_ddr_input_test"
+  top_module:  "tt_um_wokwi_407306064811090945"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.

src/project.v

@@ -79,7 +79,7 @@ module ddr_input #(parameter N=4) (input rst_n, clk, d, output q);
 
 endmodule
 
-module tt_um_ericsmi_ddr_input_test (
+module tt_um_wokwi_407306064811090945(
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path

src/tt_tb.v

@@ -17,7 +17,7 @@ always @(posedge clk) begin
   lfsr[4:0] <= rst_n ? { lfsr[3:0], ~(lfsr[4] ^ lfsr[2]) } : 5'd0; 
 end
 
-tt_um_ericsmi_ddr_input_test ericsmi_tt_um_ddr_input_test(
+tt_um_wokwi_407306064811090945 ericsmi_tt_um_ddr_input_test(
     .ui_in({8{lfsr[0]}}),  
     .uo_out(uo_out[7:0]),
     .uio_in(8'd0),

test/tb.v

@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_ericsmi_ddr_input_test user_project (
+  tt_um_wokwi_407306064811090945 user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST