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Register waccess #65

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f0e983d
register waccess to align with data
jrobrien Oct 6, 2023
8a3cf91
register waccess to align with data
jrobrien Oct 6, 2023
982a568
align waccess output with wdata
jrobrien Oct 30, 2023
3c2c8b3
change version in setup
f8-jro Jul 25, 2024
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17 changes: 15 additions & 2 deletions corsair/templates/regmap_verilog.j2
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Original file line number Diff line number Diff line change
Expand Up @@ -141,6 +141,11 @@ csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_raccess
csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_waccess
{%- endmacro %}

{#- port: bitfield write access strobe registered #}
{% macro port_bf_waccess_ff(reg, bf) %}
csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_waccess_ff
{%- endmacro %}

{#- port: bitfield lock signal #}
{% macro port_bf_lock(reg, bf) %}
csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_lock
Expand Down Expand Up @@ -280,13 +285,15 @@ end
//---------------------
{% if 'a' in bf.hardware %}
{% if 'o' in bf.hardware %}
assign {{ port_bf_waccess(reg, bf) }} = wready && {{ sig_csr_wen(reg) }};
{# assign {{ port_bf_waccess(reg, bf) }} = wready && {{ sig_csr_wen(reg) }}; #}
assign {{ port_bf_waccess(reg, bf) }} = {{ port_bf_waccess_ff(reg, bf) }};
{% endif %}
{% if 'i' in bf.hardware %}
assign {{ port_bf_raccess(reg, bf) }} = rvalid && {{ sig_csr_ren(reg) }};
{% endif %}
{% endif %}
reg {{ range_decl(bf.width - 1, bf.is_vector()) }} {{ sig_bf_ff(reg, bf) }};
reg {{ port_bf_waccess_ff(reg, bf) }};

{% if 'wo' in bf.access %}
assign {{ sig_csr_rdata(reg) }}{{ range(bf.msb, bf.lsb) }} = {{ zeros(bf.width) }};
Expand All @@ -307,7 +314,6 @@ assign {{ port_bf_ren(reg, bf) }} = {{ sig_csr_ren(reg) }} & (~{{ sig_csr_ren_ff
{% if 'w' in bf.access and 'q' in bf.hardware %}
assign {{ port_bf_wen(reg, bf) }} = {{ sig_csr_wen(reg) }};
{% endif %}

{{ always_begin(sig=sig_bf_ff(reg, bf), width=bf.width, init=bf.reset)
}} {% if 'l' in bf.hardware %}if (!{{ port_bf_lock(reg, bf) }}){% endif %} begin
{% if 's' in bf.hardware %}
Expand Down Expand Up @@ -374,6 +380,13 @@ assign {{ port_bf_wen(reg, bf) }} = {{ sig_csr_wen(reg) }};
end
end

{% if 'w' in bf.access %}
{{ always_begin(sig=port_bf_waccess_ff(reg, bf), width=1, init=0) }} begin
{{ port_bf_waccess_ff(reg, bf) }} <= wready && {{ sig_csr_wen(reg) }};
end
end
{% endif %}

{% if 'r' in bf.access and 'q' in bf.hardware %}
reg {{ sig_bf_rvalid_ff(reg, bf) }};
{{ always_begin(sig=sig_bf_rvalid_ff(reg, bf)
Expand Down
14 changes: 13 additions & 1 deletion corsair/templates/regmap_vhdl.j2
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Original file line number Diff line number Diff line change
Expand Up @@ -172,6 +172,11 @@ csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_raccess
csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_waccess
{%- endmacro %}

{#- port: bitfield write access strobe #}
{% macro port_bf_waccess_ff(reg, bf) %}
csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_waccess_ff
{%- endmacro %}

{#- port: bitfield lock signal #}
{% macro port_bf_lock(reg, bf) %}
csr_{{ reg.name.lower() }}_{{ bf.name.lower() }}_lock
Expand Down Expand Up @@ -384,7 +389,8 @@ begin
-----------------------
{% if 'a' in bf.hardware %}
{% if 'o' in bf.hardware %}
{{ port_bf_waccess(reg, bf) }} <= wready and {{ sig_csr_wen(reg) }};
{# {{ port_bf_waccess(reg, bf) }} <= wready and {{ sig_csr_wen(reg) }}; #}
{{ port_bf_waccess(reg, bf) }} <= {{ port_bf_waccess_ff(reg, bf) }};
{% endif %}
{% if 'i' in bf.hardware %}
{{ port_bf_raccess(reg, bf) }} <= rvalid and {{ sig_csr_ren(reg) }};
Expand Down Expand Up @@ -493,6 +499,12 @@ begin
{% endif %}
{{ process_end() }}

{% if 'w' in bf.access %}
{{ process_begin(sig=port_bf_waccess_ff(reg, bf), width=1, init=0)}}
{{ port_bf_waccess_ff(reg, bf) }} <= wready and {{ sig_csr_wen(reg) }};
{{ process_end() }}
{%endif%}

{% if 'r' in bf.access and 'q' in bf.hardware %}
{{ process_begin(sig=sig_bf_rvalid_ff(reg, bf)) }}
{{ sig_bf_rvalid_ff(reg, bf) }} <= {{ port_bf_rvalid(reg, bf) }};
Expand Down
2 changes: 1 addition & 1 deletion setup.py
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
import setuptools
from pkg_resources import parse_version

VERSION = "1.0.4"
VERSION = "1.0.4+waccess"


# Based on https://github.com/tulip-control/dd/blob/885a716a56e82bfee54b0178d0ce38298b85eb6a/setup.py#L68
Expand Down