build(deps): bump third_party/litex from 95b310e
to c1e4b3a
#3467
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Bumps third_party/litex from
95b310e
toc1e4b3a
.Commits
c1e4b3a
xilinx/clock: Add reset_buf parameter to allow using a buffer to route reset ...d0bb837
Merge pull request #1828 from enjoy-digital/verilog_improvements_2657252c
gen/fhdl/namer: Update copyrights.5b989bc
gen/fhdl/verilog: Switch Assign/Operator types to IntEnum.33fd774
interconnect/stream/ClockDomainCrossing: Use DUID for clock_domain id to allo...ef4235a
gen/fhdl/namer: Use _ for private functions and remove build_namespace.af508fd
gen/fhdl/namer: Improve/Simplify SignalNamespace.get_name method.9ce2922
gen/fhdl/namer: Add all_numbers to HierarchyNode to avoid hasattr use.3df23a2
gen/fhdl/namer: Avoid deep level of nesting on build_signal_name_dict_for_group.c8a96b8
gen/fhdl/namer: Add update method to HierarchyNode to replace update_hierarch...Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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