Basic CPU design with Logisim and Verilog

University of Marmara, CSE3015 2018 Fall Project

This project contains:

• Part 1 contains Assembler written in Python
• Part 2 contains Logisim design of CPU and its components
• Part 3 contains Verilog code of our CPU
• Also detailed project report can be found in repository

Detailed information:

• Data Memory.txt contains the initial values of the memory.
• Input.txt contains instructions to be executed.
• Instruction Memory.txt contains instructions in assembly format.
• Assembler.java is a assembler taking instructions from Input.txt and converting them into 5 byte long binary format instructions. (Creating Instruction Memory.txt)
• Instruction Memory.txt contains instructions in binary format.
• Project.circ file is a logic design implementation of our CPU. The file can be executed in "Logisim" design tool.
• Detailed explanation of the project is available in the ProjectReport.docx file.