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Feature/ext int improvement (#310)
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* Improved support for ext_int.

* Removed a debug message.

* Removed another debug message.

* Fixed a compilation error.

* Changed the way the clang plugin dump the integer type.

* Fixed an issue on boolean type creation when short_circuit_taf step is executed.

* Fixed a compilation dependency.

* tree_helper::Size refactoring.

* Fixed a problem of the vectorization.

* Fixed a seg fault.

* Improved vectorization support.

* Fixed a typo.

* Fixed some issues with the vectorization.

* Fixed an error with verilator simulation.

* Fixed a typo.

* Fixed a bitfield issue.

* Fixed a not supported pattern.

* Fixed another two SizeAlloc.

* Fixed another issue with SizeAlloc.

* Removed a debugging print.
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fabrizioferrandi authored Apr 6, 2024
1 parent b1b4c0e commit d12313f
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Showing 39 changed files with 403 additions and 221 deletions.
2 changes: 2 additions & 0 deletions QTCreator-PandA-GitHub.files
Original file line number Diff line number Diff line change
Expand Up @@ -1999,6 +1999,8 @@ src/design_flows/backend/ToC/source_code_writers/hls_instruction_writer.cpp
src/design_flows/backend/ToC/source_code_writers/hls_instruction_writer.hpp
src/design_flows/backend/ToC/source_code_writers/instruction_writer.cpp
src/design_flows/backend/ToC/source_code_writers/instruction_writer.hpp
src/design_flows/backend/ToC/source_code_writers/mdpi_wrapper_c_writer.cpp
src/design_flows/backend/ToC/source_code_writers/mdpi_wrapper_c_writer.hpp
src/design_flows/backend/ToDataFile/generate_fu_list.cpp
src/design_flows/backend/ToDataFile/generate_fu_list.hpp
src/design_flows/backend/ToDataFile/to_data_file_step.cpp
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8 changes: 4 additions & 4 deletions etc/clang_plugin/dumpGimple.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3264,7 +3264,7 @@ namespace llvm
case llvm::Type::IntegerTyID:
{
llvm::Type* casted_ty = const_cast<llvm::Type*>(ty);
return DL->getTypeAllocSizeInBits(casted_ty);
return DL->getTypeSizeInBits(casted_ty);
}
case llvm::Type::HalfTyID:
case llvm::Type::FloatTyID:
Expand Down Expand Up @@ -3326,7 +3326,7 @@ namespace llvm
const llvm::Type* Cty = reinterpret_cast<const llvm::Type*>(t);
bool isSigned = CheckSignedTag(Cty) || TREE_CODE(t) == GT(SIGNEDPOINTERTYPE);
llvm::Type* ty = const_cast<llvm::Type*>(NormalizeSignedTag(Cty));
auto obj_size = TREE_CODE(t) == GT(SIGNEDPOINTERTYPE) ? 32 : DL->getTypeAllocSizeInBits(ty);
auto obj_size = TREE_CODE(t) == GT(SIGNEDPOINTERTYPE) ? DL->getPointerSizeInBits() : DL->getTypeSizeInBits(ty);
auto val = isSigned ? llvm::APInt::getSignedMinValue(obj_size) : llvm::APInt::getMinValue(obj_size);
auto context = TREE_CODE(t) == GT(SIGNEDPOINTERTYPE) ? moduleContext : &ty->getContext();
return getIntegerCST(isSigned, *context, val, t);
Expand All @@ -3337,7 +3337,7 @@ namespace llvm
const llvm::Type* Cty = reinterpret_cast<const llvm::Type*>(t);
bool isSigned = CheckSignedTag(Cty) || TREE_CODE(t) == GT(SIGNEDPOINTERTYPE);
llvm::Type* ty = const_cast<llvm::Type*>(NormalizeSignedTag(Cty));
auto obj_size = TREE_CODE(t) == GT(SIGNEDPOINTERTYPE) ? 32 : DL->getTypeAllocSizeInBits(ty);
auto obj_size = TREE_CODE(t) == GT(SIGNEDPOINTERTYPE) ? DL->getPointerSizeInBits() : DL->getTypeSizeInBits(ty);
auto val = isSigned ? llvm::APInt::getSignedMaxValue(obj_size) : llvm::APInt::getMaxValue(obj_size);
if(maxValueITtable.find(t) != maxValueITtable.end())
{
Expand Down Expand Up @@ -3387,7 +3387,7 @@ namespace llvm
llvm::Type* ty = const_cast<llvm::Type*>(NormalizeSignedTag(Cty));
if(TREE_CODE(t) == GT(SIGNEDPOINTERTYPE))
{
auto obj_size = llvm::APInt(64, 32u);
auto obj_size = llvm::APInt(64, DL->getPointerSizeInBits());
if(uicTable.find(obj_size) == uicTable.end())
{
uicTable[obj_size] = assignCodeAuto(llvm::ConstantInt::get(ty->getContext(), obj_size));
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2 changes: 1 addition & 1 deletion etc/lib/technology/NC_VEC_IPs.xml
Original file line number Diff line number Diff line change
Expand Up @@ -384,4 +384,4 @@ endgenerate" VHDL_PROVIDED="begin
</circuit>
</cell>
</library>
</technology>
</technology>
2 changes: 2 additions & 0 deletions examples/IP_integration/module1.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`timescale 1ns / 1ps
module module1_IP
(input wire clock,
input wire reset,
Expand Down Expand Up @@ -65,6 +66,7 @@ module module1_IP

endmodule

`timescale 1ns / 1ps
module module1 (clock, reset, start_port, input1, input2, outputs, done_port, Min_oe_ram, Mout_oe_ram, Min_we_ram, Mout_we_ram, Min_addr_ram, Mout_addr_ram, M_Rdata_ram, Min_Wdata_ram, Mout_Wdata_ram, Min_data_ram_size, Mout_data_ram_size, M_DataRdy);
parameter BITSIZE_outputs=1, BITSIZE_Min_addr_ram=1, BITSIZE_Mout_addr_ram=1, BITSIZE_M_Rdata_ram=8, BITSIZE_Min_Wdata_ram=8, BITSIZE_Mout_Wdata_ram=8, BITSIZE_Min_data_ram_size=1, BITSIZE_Mout_data_ram_size=1;
// IN
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2 changes: 2 additions & 0 deletions examples/IP_integration/module2.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`timescale 1ns / 1ps
module module2_IP
(input wire clock,
input wire reset,
Expand Down Expand Up @@ -58,6 +59,7 @@ module module2_IP

endmodule

`timescale 1ns / 1ps
module module2 (clock, reset, start_port, input1, outputs, done_port, Min_oe_ram, Mout_oe_ram, Min_we_ram, Mout_we_ram, Min_addr_ram, Mout_addr_ram, M_Rdata_ram, Min_Wdata_ram, Mout_Wdata_ram, Min_data_ram_size, Mout_data_ram_size, M_DataRdy);
parameter BITSIZE_outputs=1, BITSIZE_Min_addr_ram=1, BITSIZE_Mout_addr_ram=1, BITSIZE_M_Rdata_ram=8, BITSIZE_Min_Wdata_ram=8, BITSIZE_Mout_Wdata_ram=8, BITSIZE_Min_data_ram_size=1, BITSIZE_Mout_data_ram_size=1;
// IN
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10 changes: 6 additions & 4 deletions src/HLS/binding/interconnection/mux_connection_binding.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,7 @@
#include "hls.hpp"
#include "hls_manager.hpp"
#include "liveness.hpp"
#include "math_function.hpp"
#include "memory.hpp"
#include "memory_symbol.hpp"
#include "multi_unbounded_obj.hpp"
Expand Down Expand Up @@ -305,8 +306,8 @@ unsigned int mux_connection_binding::address_precision(unsigned int precision, c
HLS->allocation_information->get_proxy_memory_var(fu_type);
if(var && HLSMgr->Rmem->is_private_memory(var))
{
unsigned long long int max_addr =
HLSMgr->Rmem->get_base_address(var, HLS->functionId) + tree_helper::Size(TreeM->CGetTreeReindex(var)) / 8;
unsigned long long int max_addr = HLSMgr->Rmem->get_base_address(var, HLS->functionId) +
tree_helper::SizeAlloc(TreeM->CGetTreeReindex(var)) / 8;
unsigned int address_bitsize;
for(address_bitsize = 1; max_addr > (1ull << address_bitsize); ++address_bitsize)
{
Expand Down Expand Up @@ -382,7 +383,7 @@ void mux_connection_binding::determine_connection(const vertex& op, const HLS_ma
{
unsigned long long int max_addr =
HLSMgr->Rmem->get_base_address(GET_INDEX_CONST_NODE(ref_var), HLS->functionId) +
tree_helper::Size(ref_var) / 8;
tree_helper::SizeAlloc(ref_var) / 8;
for(local_precision = 1; max_addr > (1ull << local_precision); ++local_precision)
{
;
Expand Down Expand Up @@ -1591,14 +1592,15 @@ void mux_connection_binding::create_connections()
/// connect size port
if(Prec != algn && Prec % algn)
{
Prec = std::max(8ull, resize_1_8_pow2(Prec));
HLS_manager::check_bitwidth(Prec);
determine_connection(
op, HLS_manager::io_binding_type(0, Prec), fu_obj, port_offset(2), port_index, data,
static_cast<unsigned>(object_bitsize(TreeM, HLS_manager::io_binding_type(0, Prec))));
}
else
{
const auto IR_var_bitsize = Prec != 0 ? Prec : tree_helper::Size(tn);
const auto IR_var_bitsize = tree_helper::SizeAlloc(tn);
HLS_manager::check_bitwidth(IR_var_bitsize);
unsigned int var_bitsize;
var_bitsize = static_cast<unsigned int>(IR_var_bitsize);
Expand Down
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