more generics code cleanup

src/chips/ay3891.zig

@@ -47,7 +47,7 @@ pub const Config = struct {
     bus: type,
 };
 
-pub fn AY3891(comptime cfg: Config) type {
+pub fn Type(comptime cfg: Config) type {
     return struct {
         const Self = @This();
         const Bus = cfg.bus;

src/chips/z80.zig

@@ -67,7 +67,7 @@ pub const Config = struct {
     bus: type,
 };
 
-pub fn Z80(comptime cfg: Config) type {
+pub fn Type(comptime cfg: Config) type {
     const Bus = cfg.bus;
     return struct {
         const Self = @This();

src/chips/z80ctc.zig

@@ -39,13 +39,13 @@ pub const DefaultPins = Pins{
 
 pub const Config = struct { pins: Pins, bus: type };
 
-pub fn Z80CTC(comptime cfg: Config) type {
+pub fn Type(comptime cfg: Config) type {
     assert(cfg.pins.CS[1] == cfg.pins.CS[0] + 1);
     assert(cfg.pins.ZCTO[1] == cfg.pins.ZCTO[0] + 1);
     assert(cfg.pins.ZCTO[2] == cfg.pins.ZCTO[1] + 1);
 
     const Bus = cfg.bus;
-    const Z80IRQ = z80irq.Z80IRQ(.{
+    const Z80IRQ = z80irq.Type(.{
         .pins = .{
             .DBUS = cfg.pins.DBUS,
             .M1 = cfg.pins.M1,

src/chips/z80irq.zig

@@ -17,7 +17,7 @@ pub const Config = struct {
     bus: type,
 };
 
-pub fn Z80IRQ(comptime cfg: Config) type {
+pub fn Type(comptime cfg: Config) type {
     const Bus = cfg.bus;
     return struct {
         const Self = @This();

src/chips/z80pio.zig

@@ -2,7 +2,7 @@
 const bitutils = @import("common").bitutils;
 const mask = bitutils.mask;
 const maskm = bitutils.maskm;
-const z80irg = @import("z80irq.zig");
+const z80irq = @import("z80irq.zig");
 
 /// Z80 PIO pin declarations
 pub const Pins = struct {
@@ -50,9 +50,9 @@ pub const Config = struct {
     bus: type,
 };
 
-pub fn Z80PIO(cfg: Config) type {
+pub fn Type(cfg: Config) type {
     const Bus = cfg.bus;
-    const Z80IRQ = z80irg.Z80IRQ(.{
+    const Z80IRQ = z80irq.Type(.{
         .pins = .{
             .DBUS = cfg.pins.DBUS,
             .M1 = cfg.pins.M1,

src/common/memory.zig

@@ -1,4 +1,7 @@
-//! a paged memory implementation
+//! implements a paged memory system for emulators with up to 16 bits address range
+//!
+//! NOTE: all user-provided slices must reference host memory that outlives the Memory object!
+//!
 const std = @import("std");
 const assert = std.debug.assert;
 
@@ -13,24 +16,24 @@ const assert = std.debug.assert;
 /// - for unmapped memory, the read pointer points to a special
 ///   'unmapped page' which is filled with a user-provided 'unmapped value'
 ///   (typically 0xFF), and the write pointer points to the junk page
-const Page = struct {
+pub const Page = struct {
     read: [*]const u8,
     write: [*]u8,
 };
 
-pub const ADDR_RANGE = 0x10000;
-pub const ADDR_MASK = ADDR_RANGE - 1;
+pub const Config = struct {
+    page_size: comptime_int,
+};
 
-/// implements a paged memory system for emulators with up to 16 bits address range
-///
-/// NOTE: all user-provided slices must reference host memory that outlives the Memory object!
-///
-pub fn Memory(comptime page_size: comptime_int) type {
-    assert(std.math.isPowerOfTwo(page_size));
+pub fn Type(comptime cfg: Config) type {
+    assert(std.math.isPowerOfTwo(cfg.page_size));
 
     return struct {
         const Self = @This();
 
+        pub const ADDR_RANGE = 0x10000;
+        pub const ADDR_MASK = ADDR_RANGE - 1;
+
         /// Memory init options
         pub const Options = struct {
             /// a user-provided memory area of 'page_size' as junk page
@@ -41,8 +44,8 @@ pub fn Memory(comptime page_size: comptime_int) type {
             unmapped_page: []const u8,
         };
 
-        pub const PAGE_SIZE: usize = page_size;
-        pub const PAGE_SHIFT: usize = std.math.log2_int(u16, page_size);
+        pub const PAGE_SIZE: usize = cfg.page_size;
+        pub const PAGE_SHIFT: usize = std.math.log2_int(u16, cfg.page_size);
         pub const NUM_PAGES: usize = ADDR_RANGE / PAGE_SIZE;
         pub const PAGE_MASK: usize = PAGE_SIZE - 1;
 

src/systems/bombjack.zig

@@ -1,6 +1,8 @@
 const std = @import("std");
 const assert = std.debug.assert;
 const chips = @import("chips");
+const z80 = chips.z80;
+const ay3891 = chips.ay3891;
 const common = @import("common");
 const memory = common.memory;
 const clock = common.clock;
@@ -9,8 +11,6 @@ const AudioCallback = common.glue.AudioCallback;
 const AudioOptions = common.glue.AudioOptions;
 const DisplayInfo = common.glue.DisplayInfo;
 
-const Bus = u64;
-
 // Z80 bus definitions (same for main and sound board)
 const CPU_PINS = chips.z80.Pins{
     .DBUS = .{ 0, 1, 2, 3, 4, 5, 6, 7 },
@@ -58,12 +58,13 @@ const PSG2_PINS = chips.ay3891.Pins{
 // AY IO ports are unused, to preserve pin space we'll just map them all to the same pins
 const AY_PORT = .{ 41, 42, 43, 44, 45, 46, 47, 48 };
 
-// type definitions
-const Memory = memory.Memory(0x0400);
-const Z80 = chips.z80.Z80(.{ .pins = CPU_PINS, .bus = Bus });
-const Psg0 = chips.ay3891.AY3891(.{ .pins = PSG0_PINS, .bus = Bus });
-const Psg1 = chips.ay3891.AY3891(.{ .pins = PSG1_PINS, .bus = Bus });
-const Psg2 = chips.ay3891.AY3891(.{ .pins = PSG2_PINS, .bus = Bus });
+// setup type definitions
+const Bus = u64;
+const Memory = memory.Type(.{ .page_size = 0x0400 });
+const Z80 = z80.Type(.{ .pins = CPU_PINS, .bus = Bus });
+const PSG0 = ay3891.Type(.{ .pins = PSG0_PINS, .bus = Bus });
+const PSG1 = ay3891.Type(.{ .pins = PSG1_PINS, .bus = Bus });
+const PSG2 = ay3891.Type(.{ .pins = PSG2_PINS, .bus = Bus });
 
 const getData = Z80.getData;
 const setData = Z80.setData;
@@ -230,9 +231,9 @@ pub const Bombjack = struct {
         cpu: Z80,
         bus: Bus = 0,
         tick_count: u32 = 0,
-        psg0: Psg0,
-        psg1: Psg1,
-        psg2: Psg2,
+        psg0: PSG0,
+        psg1: PSG1,
+        psg2: PSG2,
         vsync_count: u32 = 0,
         mem: Memory,
     };
@@ -279,17 +280,17 @@ pub const Bombjack = struct {
             },
             .sound_board = .{
                 .cpu = Z80.init(),
-                .psg0 = Psg0.init(.{
+                .psg0 = PSG0.init(.{
                     .tick_hz = PSG_FREQUENCY,
                     .sound_hz = @intCast(opts.audio.sample_rate),
                     .volume = 0.3,
                 }),
-                .psg1 = Psg1.init(.{
+                .psg1 = PSG1.init(.{
                     .tick_hz = PSG_FREQUENCY,
                     .sound_hz = @intCast(opts.audio.sample_rate),
                     .volume = 0.3,
                 }),
-                .psg2 = Psg2.init(.{
+                .psg2 = PSG2.init(.{
                     .tick_hz = PSG_FREQUENCY,
                     .sound_hz = @intCast(opts.audio.sample_rate),
                     .volume = 0.3,
@@ -503,16 +504,16 @@ pub const Bombjack = struct {
             //
             switch (bus & (A7 | A4)) {
                 0 => { // PSG0
-                    if (pin(bus, WR)) bus |= Psg0.BDIR;
-                    if (!pin(bus, A0)) bus |= Psg0.BC1;
+                    if (pin(bus, WR)) bus |= PSG0.BDIR;
+                    if (!pin(bus, A0)) bus |= PSG0.BC1;
                 },
                 A4 => { // PSG1
-                    if (pin(bus, WR)) bus |= Psg1.BDIR;
-                    if (!pin(bus, A0)) bus |= Psg1.BC1;
+                    if (pin(bus, WR)) bus |= PSG1.BDIR;
+                    if (!pin(bus, A0)) bus |= PSG1.BC1;
                 },
                 A7 => { // PSG2
-                    if (pin(bus, WR)) bus |= Psg2.BDIR;
-                    if (!pin(bus, A0)) bus |= Psg2.BC1;
+                    if (pin(bus, WR)) bus |= PSG2.BDIR;
+                    if (!pin(bus, A0)) bus |= PSG2.BC1;
                 },
                 else => {},
             }
@@ -527,7 +528,7 @@ pub const Bombjack = struct {
 
             // clear AY control bits (this cannot happen each CPU tick because
             // the AY chips are clocked at half frequency and might miss them)
-            bus &= ~(Psg0.BDIR | Psg0.BC1 | Psg1.BDIR | Psg1.BC1 | Psg2.BDIR | Psg2.BC1);
+            bus &= ~(PSG0.BDIR | PSG0.BC1 | PSG1.BDIR | PSG1.BC1 | PSG2.BDIR | PSG2.BC1);
 
             if (board.psg0.sample.ready) {
                 const s = board.psg0.sample.value + board.psg1.sample.value + board.psg2.sample.value;

src/systems/namco.zig

@@ -68,8 +68,8 @@ const Z80_PINS = z80.Pins{
 };
 
 // setup types
-const Z80 = z80.Z80(.{ .pins = Z80_PINS, .bus = Bus });
-const Memory = memory.Memory(0x400);
+const Z80 = z80.Type(.{ .pins = Z80_PINS, .bus = Bus });
+const Memory = memory.Type(.{ .page_size = 0x400 });
 
 const getAddr = Z80.getAddr;
 const getData = Z80.getData;

tests/ay3891.test.zig

@@ -2,9 +2,9 @@ const expect = @import("std").testing.expect;
 const expectApproxEqAbs = @import("std").testing.expectApproxEqAbs;
 const ay3891 = @import("chipz").chips.ay3891;
 
-const AY38910 = ay3891.AY3891(.{ .model = .AY38910, .pins = ay3891.DefaultPins, .bus = u32 });
-const AY38912 = ay3891.AY3891(.{ .model = .AY38912, .pins = ay3891.DefaultPins, .bus = u32 });
-const AY38913 = ay3891.AY3891(.{ .model = .AY38913, .pins = ay3891.DefaultPins, .bus = u32 });
+const AY38910 = ay3891.Type(.{ .model = .AY38910, .pins = ay3891.DefaultPins, .bus = u32 });
+const AY38912 = ay3891.Type(.{ .model = .AY38912, .pins = ay3891.DefaultPins, .bus = u32 });
+const AY38913 = ay3891.Type(.{ .model = .AY38913, .pins = ay3891.DefaultPins, .bus = u32 });
 
 const BDIR = AY38910.BDIR;
 const BC1 = AY38910.BC1;

tests/memory.test.zig

@@ -2,7 +2,7 @@ const expect = @import("std").testing.expect;
 const memory = @import("chipz").common.memory;
 
 const PAGE_SIZE = 4096;
-const Memory = memory.Memory(PAGE_SIZE);
+const Memory = memory.Type(.{ .page_size = PAGE_SIZE });
 const options = Memory.Options{
     .junk_page = &junk_page,
     .unmapped_page = &unmapped_page,
@@ -37,7 +37,7 @@ test "read/write unmapped" {
 }
 
 test "map ram page sized" {
-    var mem = [_]u8{0} ** memory.ADDR_RANGE;
+    var mem = [_]u8{0} ** Memory.ADDR_RANGE;
     var m = Memory.init(options);
     m.mapRAM(0x0000, 0x1000, mem[0..0x1000]);
     m.mapRAM(0x2000, 0x1000, mem[0x1000..0x2000]);
@@ -62,7 +62,7 @@ test "map ram page sized" {
 }
 
 test "map ram multi-page sized" {
-    var mem = [_]u8{0} ** memory.ADDR_RANGE;
+    var mem = [_]u8{0} ** Memory.ADDR_RANGE;
     var m = Memory.init(options);
     m.mapRAM(0x0000, 0x4000, mem[0..0x4000]);
     m.mapRAM(0x8000, 0x4000, mem[0x4000..0x8000]);
@@ -98,7 +98,7 @@ test "map rom" {
 }
 
 test "map separate" {
-    var mem = [_]u8{0} ** memory.ADDR_RANGE;
+    var mem = [_]u8{0} ** Memory.ADDR_RANGE;
     var m = Memory.init(options);
     m.mapRW(0xC000, rom.len, &rom, mem[0x1000 .. 0x1000 + rom.len]);
     try expect(m.rd(0xC023) == 0x23);
@@ -113,7 +113,7 @@ test "map separate" {
 }
 
 test "map / unmap" {
-    var mem = [_]u8{0} ** memory.ADDR_RANGE;
+    var mem = [_]u8{0} ** Memory.ADDR_RANGE;
     var m = Memory.init(options);
     m.mapRAM(0x0000, 0x1000, mem[0..0x1000]);
     m.wr(0x0000, 0x23);

tests/z80ctc.test.zig

@@ -62,8 +62,8 @@ const Z80CTCPins = z80ctc.Pins{
 };
 
 const Bus = u64;
-const Z80 = z80.Z80(.{ .pins = Z80Pins, .bus = Bus });
-const Z80CTC = z80ctc.Z80CTC(.{ .pins = Z80CTCPins, .bus = Bus });
+const Z80 = z80.Type(.{ .pins = Z80Pins, .bus = Bus });
+const Z80CTC = z80ctc.Type(.{ .pins = Z80CTCPins, .bus = Bus });
 
 const setData = Z80.setData;
 const getData = Z80.getData;

tests/z80int.zig

@@ -14,7 +14,7 @@ const pinsAll = chipz.common.bitutils.pinsAll;
 
 const T = assert;
 const Bus = u64;
-const Z80 = z80.Z80(.{ .pins = z80.DefaultPins, .bus = Bus });
+const Z80 = z80.Type(.{ .pins = z80.DefaultPins, .bus = Bus });
 
 var cpu: Z80 = undefined;
 var bus: Bus = 0;

tests/z80pio.test.zig

@@ -4,7 +4,7 @@ const chipz = @import("chipz");
 const z80pio = chipz.chips.z80pio;
 
 const Bus = u64;
-const Z80PIO = z80pio.Z80PIO(.{ .pins = z80pio.DefaultPins, .bus = Bus });
+const Z80PIO = z80pio.Type(.{ .pins = z80pio.DefaultPins, .bus = Bus });
 
 const setData = Z80PIO.setData;
 
@@ -55,3 +55,10 @@ test "set input/output mode" {
     _ = pio.tick(setData(CE | IORQ | BASEL | CDSEL, (@as(u8, MODE.INPUT) << 6) | 0x0F));
     try expect(pio.ports[PORT.B].mode == MODE.INPUT);
 }
+
+test "set port A to bidirectional" {
+    var pio = Z80PIO.init();
+
+    _ = pio.tick(setData(CE | IORQ | CDSEL, (@as(u8, MODE.BIDIRECTIONAL) << 6) | 0x0F));
+    try expect(pio.ports[PORT.A].mode == MODE.BIDIRECTIONAL);
+}

tests/z80test.zig

@@ -5,7 +5,7 @@ const chipz = @import("chipz");
 const z80 = chipz.chips.z80;
 const pin = chipz.common.bitutils.pin;
 
-const Z80 = z80.Z80(.{ .pins = z80.DefaultPins, .bus = u64 });
+const Z80 = z80.Type(.{ .pins = z80.DefaultPins, .bus = u64 });
 
 const A = Z80.A;
 const F = Z80.F;

tests/z80timing.zig

@@ -12,7 +12,7 @@ const pin = chipz.common.bitutils.pin;
 
 const T = assert;
 const Bus = u64;
-const Z80 = z80.Z80(.{ .pins = z80.DefaultPins, .bus = Bus });
+const Z80 = z80.Type(.{ .pins = z80.DefaultPins, .bus = Bus });
 
 var cpu: Z80 = undefined;
 var bus: Bus = 0;

tests/z80zex.zig

@@ -12,7 +12,7 @@ const z80 = chipz.chips.z80;
 const pin = chipz.common.bitutils.pin;
 
 const Bus = u64;
-const Z80 = z80.Z80(.{ .pins = z80.DefaultPins, .bus = Bus });
+const Z80 = z80.Type(.{ .pins = z80.DefaultPins, .bus = Bus });
 const CTRL = Z80.CTRL;
 const M1 = Z80.M1;
 const ABUS = Z80.ABUS;