Software
The OBDH board has a MSP430 microcontroller that manages the others sub-modules in the board. This page describes the developed software for this device.
The programming language used is C. All software was developed in the Code Composer Studio IDE (a.k.a. CCS). To learn more about how to install and configure CCS go to the Toolchain Setup page.
OBDH module has to do many tasks, such interfacing peripherals and other MCUs, over distinct protocols and time requirements. Because of that, it needs a Real Time Operating System to assure that it will deal with its deadlines, even under a fault in some task routine. The RTOS chosen is FreeRTOS (v9.0.0), since it is designed for embedded systems and it was already validated in space applications.
The software was made to have some abstraction layers. This is reached using drivers to manage internal peripherals, such as GPIO, watchdog timers, timers, clocks, USCIs and ADCs. The following figure shows the software architecture.
The OBDH software consists in a initialization (boot, antenna deployment, tasks creation) and a execution (enable the operating system to run). The description is below and the flowchart can be access here.
- Boot
- Setup Hardware
- Watchdog configuration
- Clocks configuration
- Serial Interfaces configuration (I2C, SPI, UART)
- ADC configuration
- Other GPIO configuration
- Update the reset counter and reset cause
- Restore the time counter
- Setup Hardware
- Deploy antenna
- Create tasks
- Store data
- Ground Communications
- Housekeeping
- Reset Watchdog timers
- IMU interface
- Solar panels interface
- EPS interface
- Beacon interface
- Payload 1 interface
- Payload 2 interface
- Start scheduler
After each reset, the Boot code will run. Until this point, none GPIO could be used, the clock is the default internal clock (1 MHz) and none task will be running. The next sections presents the functions present in the Boot. The flowcharts can be access here.
In this function, the internal and external watchdog timers are setup. The watchdog timeouts are:
- Internal: 16 seconds (defined in software);
- External: 1.6 seconds (defined in hardware).
The MSP430x6xx family has 3 system clocks: Master Clock (MCLK), Subsytem Master Clock (SMCLK) and Auxiliary Clock (ACLK). Sets the core voltage of the MSP430 to match the desired operation clock. Enable the 2 external crystals (XT1 and XT2). Setup the internal oscillator (DCO). Test if the XT1, XT2 and DCO are working fine. The table below shows the configuration of the 3 system clocks:
| Clock Name | Clock Source | Alternative Clock Source | Prescaler | Clock Frequency |
|---|---|---|---|---|
| MCLK | XT2 (32 MHz) | DCO (32 MHz) | 2 | 16 MHz |
| SMCLK | XT2 (32 MHz) | DCO (32 MHz) | 2 | 16 MHz |
| ACLK | XT1 (32,768 KHz) | REFO (32,768 KHZ) | 1 | 32,768 KHz |
The OBDH main characteristic is concentrate and manage the data flow. Because of that, the definition of the communication interfaces are a important stage of the cubesat.The MSP430x6xx family has 6 Universal Serial Communication Interfaces (USCIs), in hardware, that can be setup to operate as I2C, SPI or UART interfaces. Besides that, there is a software implementation of the SPI protocol , allowing to use 1 USCI for something else.
The table below shows the configuration of the 3 I2C interfaces:
| MSP430 Interface | Clock Source | Mode | Slave Address Length | Prescaler | Data Rate | Connect with | |
|---|---|---|---|---|---|---|---|
| I2C_0 | USCI_B0 | SMCLK | Master | 7 bits | 160 | 100 kbps | EPS, Payloads |
| I2C_1 | USCI_B1 | SMCLK | Master | 7 bits | 160 | 100 kbps | IMUs |
| I2C_2 | USCI_B2 | SMCLK | Master | 7 bits | 160 | 100 kbps | Antenna Deployment System |
The table below shows the configuration of the 3 SPI (2 using specific hardware and 1 using software) interfaces:
| MSP430 Interface | Clock Source | Mode | Length | Phase | Polarity | Endianness | Prescaler | Data Rate | Connect with | |
|---|---|---|---|---|---|---|---|---|---|---|
| SPI_0 | USCI_A0 | SMCLK | Master | 8 bits | High | Low | MSB | 40 | 400 kbps | Main Radio |
| SPI_1 | USCI_A1 | SMCLK | Master | 8 bits | High | Low | MSB | 40 | 400 kbps | SD card, Memories, Solar Panels |
| SSPI | Made in Software | Master | 8 bits | Low | Low | MSB | 50 kbps | Beacon MCU |
The table below shows the configuration of the UART interface:
| MSP430 Interface | Clock Source | Data bits | Stop bits | Parity | Data rate | |
|---|---|---|---|---|---|---|
| UART_0 | USCI_A2 | SMCLK | 8 | 1 | None | 9600 bps |
To use the Analog-to-Digital Converter (ADC) it is necessary to setup the voltage references. As positive reference is used a Low Noise Voltage Reference IC, suppling 3.0V. As negative reference, the ground (0V) is used. The respective ADC channels connected to the sensors are shown in the table below:
| Sensor | Channel | Acquisition circuit |
|---|---|---|
| +X-face Sun Sensor | 0 | Photodiode (in solar panel) + OpAmp |
| +Y-face Sun Sensor | 1 | Photodiode (in solar panel) + OpAmp |
| +Z-face Sun Sensor | 2 | Photodiode (in solar panel) + OpAmp |
| OBDH Current | 3 | Shunt resistor + OpAmp |
| OBDH Supply Voltage | 4 | Voltage resistor (1/2) + OpAmp |
| MSP430 Temperature | 10 | MSP430 internal sensor |
To assure that some modules will be shutdown after a startup sequence, some GPIOs, connected to main radio and microSD, for instance, are setup.
The OBDH has a reset counter, in a way to know when a reset occurs, how many frequent they happen and what is it cause. This is useful to analyze the behavior of the system during different conditions and the efficiency of the fault tolerance methods.
Since resets are expected in the lifetime of any satellite, it is necessary to count the time continuously regardless of any event. The counter is stored in a non-volatile-memory at each minute, so the error after a reset is no more than 1 minute. This function reads the memory and restore the counter to the proper variable.
To communicate with Earth, the satellite has a four monopoles antenna, two for VHF(145,9 MHz) and two for UHF(437,9 MHz), that is controlled by OBDH in redundancy with Beacon. The antenna opening system independently communicates with this modules through i2c channels. After the hibernation period of 45 minutes, the antenna need to be deployed and establish communication with the FloripaSat ground station. So, the OBDH is responsible for execute the deployment sequence that consists in arm the system, deploy each monopole, ensure the deployment and report the antenna status. The entire deployment process is described in flowcharts here.
FreeRTOS task scheduler can be setup to work in preemptive or cooperative mode. For OBDH, the preemptive mode was chosen. In preemptive mode a task can be interrupted in the middle of it execution, because of an OS event, for instance. In cooperative mode a task just leave the processor when it finishes it execution. Other way is if a task request to leave the processor. "Leave the processor" means stop to use it, which let it free to another tasks. When the processor is free, the next task to use it is the next in a queue, ordered by its priorities. So, the most important tasks may be at the beginning of the queue. This allows us to overweight the mandatory jobs, to assure that a fault in a less relevant task do not compromise the mission. When a task be ready again to executes, it is putted in the queue, according its priority.
The next subsections describe the functionality and behavior of each OBDH's task. They are arranged in order of priority, in the RTOS context, from highest to lowest. Also, all the tasks are described in flowcharts here.
A strategy to avoid a deadlock (software lock in some code stretch) 2 watchdog is used: 1 internal and 1 external. This task will run periodically and reset the watchdog timers, so, if a lock occurs, the timer reset will not happen, the counter will overflow and the watchdog will reset the MCU. There are 2 watchdog to bring redundancy for the system.
Handle the ground-space communications. To transmit, assemble the data (sensors data, current time, reset events, received messages, peripheral status, among others) and send, over SPI protocol, to the radio transceiver. In a reception, decodes the payload of the packet, verify its authenticity and operates according the received command.
This task is responsible to maintain the proper functioning of the OBDH. Its functions are listed below:
- Read the MSP's internal sensors. The internal temperature sensor, the supply voltage and the current consumption is read over the internal ADC;
- Read system status: verify if the communication with EPS, Beacon, Payloads, IMUs and Memories are working, read the reset counter and last reset cause and read the clocks fault flags;
- Update the time counter;
- Count the time to return to Normal Mode after receiving a Shutdown Command;
- Do a periodic reset (every 12 hours).
To avoid that a reset causes lost of data, the data persistence is made on a non-volatile memory. Then (in Ground Communications task) this data could be sent over downlink. The connection with the non-volatile memory is over a SPI interface. This task read the data sent from other tasks over message queues.
This task is responsible to trade messages with the EPS module. This communication is done over I2C protocol. The purpose of this message could be: sensors data trading, notify to each other about its current status, do handshaking about some necessary shutdown, among others integration commands.
This task is responsible to trade messages with the Beacon module. This communication is done over SPI protocol, implemented in software. The purpose of the messages could be: send some data to be transmitted along Beacon signal, warn Beacon MCU about a Shutdown command or request antenna usage.
Read the 2 on-board IMUs. Each IMU has a 3-axis Accelerometer, 3-axis Gyroscope, 3-axis Magnetometer and 1 temperature sensor. This data is necessary to allow the Attitude Control in ADCS module. The both IMU are in an I2C bus.
Read the solar panels sensors over a SPI interface. Each solar panel (there are 3 interfaces at all) have an 1-axis gyroscope, a sun sensor and a temperature sensor.
The saved data was described in the table below:
| Data | Length [bytes] |
|---|---|
| Packet Flags | 2 |
| OBDH Status | 6 |
| IMU | 24 |
| OBDH Misc | 6 |
| OBDH Uptime | 4 |
| Solar Panels Sensors | 12 |
| Main Radio | 19 |
| Solar Panels | 18 |
| EPS Misc | 8 |
| Battery Monitor | 21 |
| Temperatures | 21 |
| Energy Level | 1 |
| Australia | 40 |
| Joinville | 7 |
| TOTAL | 187 |
The total amount of data of 1 packet is 189 bytes (at this moment, but it can change some few bytes). Some SD/uSD cards has 512 bytes of data block size. The read and write operations are done block by block. To avoid future changes in the code if the packet size changes a few. Then, as a project decision, the data will be saved on the non-volatile memory 1 package per block. Whereas a write frequency of 1 Hz (1 package[512 bytes] per second)), in a 2GB memory (current size, but could be increased), the time until fill all the capacity is calculated by:
Then, the storage capacity is not a bottleneck, since the data acquisition by the ground segment there will rarely be a day without trying to communicate and download the data. Once the data was downloaded, the used memory can be overwritten by new data, by a cyclic scheme on memory. To know more about how to retrieve the telemetry data go to the page "Retrieving the data".
There is a 32-bit counter stored in the Memory Segment B of MSP430. This counter will be incremented each time that a minute was completed in power on mode. Because there are many write and erase operations in the memory, to avoid possible damages in the memory, the counter (4 bytes) will be stored along 32 sequential positions of the Segment B (128 bytes). Once the position reach the last address of Segment B, the next write in occurs in the beginning of the segment, composing a circular memory.
There is a 24-bit counter stored in the Memory Segment A of MSP430. This counter will be incremented each time that a reset occurs in the OBDH MCU. Within this counter, there is a 8-bit value meaning the OBDH MCU last reset cause. The table below shows the reset cause meanings:
| Value | Reset Cause |
|---|---|
| 0x02 | Brownout (BOR) (highest priority) |
| 0x04 | RST/NMI (BOR) |
| 0x06 | PMMSWBOR (BOR) |
| 0x08 | Wakeup from LPMx.5 (BOR) |
| 0x0A | Security violation (BOR) |
| 0x0C | SVSL (POR) |
| 0x0E | SVSH (POR) |
| 0x10 | SVML_OVP (POR) |
| 0x12 | SVMH_OVP (POR) |
| 0x14 | PMMSWPOR (POR) |
| 0x16 | WDT time out (PUC) |
| 0x18 | WDT password violation (PUC) |
| 0x1A | Flash password violation (PUC) |
| 0x1E | PERF peripheral/configuration area fetch (PUC) |
| 0x20 | PMM password violation (PUC) |
There is a 8-bit value that refers to the current operation mode and energy level. This value is stored in the first byte of Memory Segment C. The upper nibble refers to current operation (1-4) and the lower nibble refers to the energy level (1-4). The table below shows the 2 nibbles meaning:
| Value | Operation Mode |
|---|---|
| 0x1X | Full Operation |
| 0x2X | Telecommand |
| 0x3X | Shutdown |
| 0x4X | Antenna deployment |
| Value | Energy Level |
|---|---|
| 0xX1 | Level 1 |
| 0xX2 | Level 2 |
| 0xX3 | Level 3 |
| 0xX4 | Level 4 |
Along with the operation mode and energy level byte there is a 32-bit unsigned integer value that relates to the time, in minutes, since the system came into the actual state. This value is stored starting from the 5º byte of the Memory Segment C, 4 bytes after the current operation and energy mode address.