Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Updated Alveo U250 Constraints for Timing Issue #104

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
+6 −6
Open

Updated Alveo U250 Constraints for Timing Issue #104

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions hw/constraints/u250/shell/synth/u250_shell_base.xdc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,5 +2,5 @@
create_clock -period 4.000 [get_ports xclk]

# CMAC clocks
create_clock -period 3.103 [get_ports gt0_refclk_p]
create_clock -period 3.103 [get_ports gt1_refclk_p]
create_clock -period 6.4 [get_ports gt0_refclk_p]
create_clock -period 6.4 [get_ports gt1_refclk_p]
4 changes: 2 additions & 2 deletions hw/constraints/u250/static/impl/u250_static_base.xdc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,5 +4,5 @@ set_operating_conditions -design_power_budget 160
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design];

# CMAC clocks
create_clock -period 3.103 -name gt0_refclk_p [get_ports gt0_refclk_p];
create_clock -period 3.103 -name gt1_refclk_p [get_ports gt1_refclk_p];
create_clock -period 6.4 -name gt0_refclk_p [get_ports gt0_refclk_p];
create_clock -period 6.4 -name gt1_refclk_p [get_ports gt1_refclk_p];
4 changes: 2 additions & 2 deletions hw/constraints/u250/static/synth/u250_static_synth.xdc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
create_clock -period 10.000 [get_ports pcie_clk_clk_p];

# CMAC clocks
create_clock -period 3.103 [get_ports gt0_refclk_p];
create_clock -period 3.103 [get_ports gt1_refclk_p];
create_clock -period 6.4 [get_ports gt0_refclk_p];
create_clock -period 6.4 [get_ports gt1_refclk_p];

# Debug
connect_debug_port inst_static/inst_debug_hub/inst/xsdbm/clk [get_nets inst_static/pclk]