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Getting Started Guide

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David Sidler edited this page Dec 11, 2016 · 3 revisions

Welcome to the Getting Started Guide!

This guide covers

  • System Requirements
  • Downloading the code repository
  • Installation
  • Testing the example project

System Requirements

  • Xilinx Vivado HLS 2015.1 (Due to a bug in the HLS DATAFLOW pragma newer version are not working)
  • Xilinx Vivado 2016.2 (most recent version should work)
  • License for Xilinx 10G MAC IP
  • Linux OS
  • Xilinx VC709 or ADM-PCIE-7V3 FPGA card from Alpha Data

Downloading the code repository

On your machine, change to the desired directory and execute the following command:

git clone git@github.com:NetFPGA/NetFPGA-SUME-live.git

Installation

Make sure that Xilinx Vivado HLS 2015.1 is in your PATH.

Navigate to tcp_ip/scripts:

cd tcp_ip/scripts

Execute the make script:

./make_tcp_ip.sh

Make sure that Vivado (2016.2) is set in your PATH.

Create the example project for your board.

For the Xilinx VC709:

vivado -mode batch -source create_vc709_proj.tcl

For the Alpha DATA ADM-PCIE-7V3:

vivado -mode batch -source reate_adm7v3_proj.tcl

After the previous command executed, a Vivado project will be created and the Vivado GUI is started.

Set the address, DefaultGateway and MAC address if required at the top of the tcp_ip_top.v file

Click "Generate Bitstream" to generate a bitstream for the FPGA.

Testing the example project

Deploy the generated .bit file on the Xilinx VC709 or Alpha Data 7V3 board. This .bit file loops back both UDP and TCP packetssent to the FPGA.

Connect the 10G ETH port on another PC to the 10G ETH port on the FPGA board and set the IP address of this PC 10G to be in the same subnet as the FPGA.

From the PC console enter following command to check if you can ping the FPGA successfully by running following command: ping

Navigate to tcp_ip/scripts and enter following command to send packets which will be looped back.

python ./client_length_mt_fixed_char.py --ip=<FPGA-ip-address>

This python script basically will create two sessions and send packets to the TOE and the close the session.

If you run following command, UDP packets will be looped back.

python ./client_fixed_length.py --ip=<FPGA-ip-address>
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