[codegen] reject zero-bit literals, they are invalid in verilog

[cdleary]

• Reject zero-width VAST literals instead of emitting illegal sized Verilog like 0'h0
• Split literal construction into a checked Literal(...) API and a LiteralOrDie(...) convenience wrapper, then propagate status through the relevant codegen and C API paths
• Add focused tests for VAST literal rejection and node-to-VAST lowering, while preserving existing zero-width elision behavior where zero-width values should disappear instead of being materialized

Just a context note, this is observable if you fiddle with the passes via the new pass flag facilities, you just get errors in downstream tools like yosys since SV doesn't support this construct, erroring up front in the XLS tooling that we can't codegen verilog directly from the IR is more sound.