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DTL H2000 protocol
The reset sequence of the DTL-H2000 happens in two steps, with one argument. The argument to the RESETPS.EXE binary can be 0, 1 or 2, and they are representing the sort of reset being performed by the board. Usually, 1 is used and represent resetting into the DECI console.
The simplest form of reset performed by the RESETPS.EXE binary is done through these two operations on the ISA bus:
OUT [baseAddr + 6], [resetCommand]
OUT [baseAddr + 4], 0x71
All signs point to the fact that the controller PLD will hold the reset command value, and it'll be read at boot time by the bios. Therefore, the first OUT is most likely a write into that PLD's, which then will store it into a hardware register readable from the SBUS of the MIPS CPU.
It is likely that the second OUT will trigger a reset somehow, most likely on the same PLD, since it's the one connected to the data bus.
The DEXBIOS.COM TSR also does one extra write to the ISA bus:
OUT [baseAddr + 5], 1