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add ephy support for t21
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@gtxaspec
gtxaspec committed May 4, 2024
1 parent 7587bba commit bd73e73
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157 changes: 157 additions & 0 deletions drivers/net/SynopGMAC_Dev.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1269,6 +1269,28 @@ s32 synopGMAC_check_phy_init(synopGMACdevice * gmacdev) {
u16 id1 = 0;
u16 id2 = 0;

#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_OMNI)
/* enable MII mode */
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase, 0x12, &data);
if(status)
return status;
data &= ~(0x3<<14);
data |= (0x00<<14);
status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase, 0x12 , data);
if(status)
return status;
#if 0
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase, 0x00, &data);
if(status)
return status;
data &= ~(0x1<<8 | 0x1<<12 | 0x1<<13);
data |= (0x1<<8 | 0x1<<13);
status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase, 0x00 , data);
if(status)
return status;
#endif
#endif

status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, &data);
if (status)
return status;
Expand Down Expand Up @@ -1299,6 +1321,69 @@ s32 synopGMAC_check_phy_init(synopGMACdevice * gmacdev) {
return status;

#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_DM9161) || (CONFIG_NET_PHY_TYPE == PHY_TYPE_8710A) || (CONFIG_NET_PHY_TYPE == PHY_TYPE_IP101G)
/* RTL8201F */
if ((0x1c == id1) && (0xc816 == id2)) {
if((data & 1) == 0){
TR("No Link\n");
gmacdev->LinkState = LINKDOWN;
return -ESYNOPGMACPHYERR;
}
else{
gmacdev->LinkState = LINKUP;
TR("Link UP\n");
}
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,0x0, &data);
if(status)
return status;
if(data&0x0100) {
gmacdev->DuplexMode = FULLDUPLEX;
}
else {
gmacdev->DuplexMode = HALFDUPLEX;
}
if(data&0x2000) {
gmacdev->Speed = SPEED100;
}
else {
gmacdev->Speed = SPEED10;
}
}
else
{
if((data & 1) == 0){
TR("No Link\n");
gmacdev->LinkState = LINKDOWN;
return -ESYNOPGMACPHYERR;
}
else{
gmacdev->LinkState = LINKUP;
TR("Link UP\n");
}
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,0x1f, &data);
if(status)
return status;
if((data&(6<<2))==(6<<2)) {
gmacdev->DuplexMode = FULLDUPLEX;
gmacdev->Speed = SPEED100;
}
else if((data&(2<<2))==(2<<2)) {
gmacdev->DuplexMode = HALFDUPLEX;
gmacdev->Speed = SPEED100;

}
else if((data&(5<<2))==(5<<2)) {
gmacdev->DuplexMode = FULLDUPLEX;
gmacdev->Speed = SPEED10;

}
else if((data&(1<<2))==(1<<2)) {
gmacdev->DuplexMode = HALFDUPLEX;
gmacdev->Speed = SPEED10;
}

}

#elif (CONFIG_NET_PHY_TYPE == PHY_TYPE_DM9161) || (CONFIG_NET_PHY_TYPE == PHY_TYPE_8710A) || (CONFIG_NET_PHY_TYPE == PHY_TYPE_IP101G)
/* RTL8201F */
if ((data & 1) == 0) {
TR("No Link\n");
Expand Down Expand Up @@ -1359,6 +1444,78 @@ s32 synopGMAC_check_phy_init(synopGMACdevice * gmacdev) {
} else {
gmacdev->DuplexMode = HALFDUPLEX;
}
#elif (CONFIG_NET_PHY_TYPE == PHY_TYPE_OMNI)
if ((0x1c == id1) && (0xc816 == id2)) {
if((data & 0x4) == 0){
TR("No Link\n");
gmacdev->LinkState = LINKDOWN;
return -ESYNOPGMACPHYERR;
}
else{
gmacdev->LinkState = LINKUP;
TR("Link UP\n");
}
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase, 0x1f, &data);
if(status)
return status;
if(data&0x10) {
gmacdev->DuplexMode = FULLDUPLEX;
}
else {
gmacdev->DuplexMode = HALFDUPLEX;
}
if(data&0x8) {
gmacdev->Speed = SPEED100;
}
else {
gmacdev->Speed = SPEED10;
}
}
else
{
if((data & 1) == 0){
TR("No Link\n");
gmacdev->LinkState = LINKDOWN;
return -ESYNOPGMACPHYERR;
}
else{
gmacdev->LinkState = LINKUP;
TR("Link UP\n");
}
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,0x1f, &data);
if(status)
return status;
if((data&(6<<2))==(6<<2)) {
gmacdev->DuplexMode = FULLDUPLEX;
gmacdev->Speed = SPEED100;
printf("====> PHY 100M full\n");
}
else if((data&(2<<2))==(2<<2)) {
gmacdev->DuplexMode = HALFDUPLEX;
gmacdev->Speed = SPEED100;

}
else if((data&(5<<2))==(5<<2)) {
gmacdev->DuplexMode = FULLDUPLEX;
gmacdev->Speed = SPEED10;

}
else if((data&(1<<2))==(1<<2)) {
gmacdev->DuplexMode = HALFDUPLEX;
gmacdev->Speed = SPEED10;
}

}
#if 0
{
int index = 0;
for(index = 0; index < 32; index++){
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase, index, &data);
printf("PHY reg = %d, value = 0x%04x\n", index, data);
}
}
#endif

#endif //CONFIG_NET_PHY_TYPE
} else {
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_STATUS_REG, &data);
Expand Down
171 changes: 171 additions & 0 deletions drivers/net/jz4775-9161.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -521,11 +521,38 @@ int jz_net_initialize(bd_t *bis)
u16 data;
s32 status = -ESYNOPGMACNOERR;

#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_OMNI)
clk_set_rate(MACPHY,25000000);

cpm_mphyc = read_cpm_mphyc();
cpm_mphyc |= (0x1<<21);
write_cpm_mphyc(cpm_mphyc);

udelay(50000);
*(volatile unsigned int *)(0xb0011018) = 1<<7 | 1 << 15;
*(volatile unsigned int *)(0xb0011028) = 1<<7 | 1 << 15;
*(volatile unsigned int *)(0xb0011034) = 1<<7 | 1 << 15;
*(volatile unsigned int *)(0xb0011048) = 1<<7 | 1 << 15;

#if 0
/* PB13 PB14 fun0 */
*(volatile unsigned int *)(0xb0011018) = 1<<13 | 1 << 14;
*(volatile unsigned int *)(0xb0011028) = 1<<13 | 1 << 14;
*(volatile unsigned int *)(0xb0011038) = 1<<13 | 1 << 14;
*(volatile unsigned int *)(0xb0011048) = 1<<13 | 1 << 14;
#endif
#else /* other PHY type */
clk_set_rate(MACPHY,50000000);
udelay(50000);
#endif /* PHY_TYPE_OMNI */

#ifndef PHY_TYPE_OMNI
#ifndef CONFIG_FPGA
clk_set_rate(MACPHY, CONFIG_GMAC_PHY_RATE);
udelay(50000);
#endif

#endif
#if defined (CONFIG_T10) || defined (CONFIG_T20) || defined (CONFIG_T30) || defined (CONFIG_T21) || defined (CONFIG_T23) || defined (CONFIG_T31)
/* initialize gmac gpio */
gpio_set_func(GPIO_PORT_B, GPIO_FUNC_0, 0x1EFC0);
Expand All @@ -536,6 +563,7 @@ int jz_net_initialize(bd_t *bis)
gmacdev->DmaBase = JZ_GMAC_BASE + DMABASE;
gmacdev->MacBase = JZ_GMAC_BASE + MACBASE;

#ifndef CONFIG_FPGA
#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_IP101G)
/* gpio reset IP101G */
#ifdef CONFIG_GPIO_IP101G_RESET
Expand Down Expand Up @@ -572,10 +600,148 @@ int jz_net_initialize(bd_t *bis)
gpio_direction_output(CONFIG_GPIO_8710A_RESET, !CONFIG_GPIO_8710A_RESET_ENLEVEL);
mdelay(10);
udelay(100000);
#elif (CONFIG_NET_PHY_TYPE == PHY_TYPE_IP101G)

/* enable ext phy */
cpm_mphyc = read_cpm_mphyc();
cpm_mphyc &= ~(0x3<<22);
write_cpm_mphyc(cpm_mphyc);

/* power on IP101G */
#ifdef CONFIG_GPIO_IP101G_POWER
gpio_direction_output(CONFIG_GPIO_IP101G_POWER, CONFIG_GPIO_IP101G_POWER_ENLEVEL);
mdelay(10);
#endif/*CONFIG_GPIO_IP101G_POWER*/

/* reset IP101G */
#ifdef CONFIG_GPIO_IP101G_RESET
gpio_direction_output(CONFIG_GPIO_IP101G_RESET, CONFIG_GPIO_IP101G_RESET_ENLEVEL);
mdelay(50);
//gpio_direction_output(32*1+13, 1);

gpio_direction_output(CONFIG_GPIO_IP101G_RESET, !CONFIG_GPIO_IP101G_RESET_ENLEVEL);
mdelay(10);
#endif/*CONFIG_GPIO_IP101G_RESET*/
#elif (CONFIG_NET_PHY_TYPE == PHY_TYPE_OMNI)
{
u32 status = 0;
u16 data = 0;
*(volatile unsigned int *)(0xB0000050) = 0xc8007016;
/* reset PHY */
int retry_cnt = 1000;
u32 cpm_mphyc_rst = 0;
/* enable internal phy */
cpm_mphyc = read_cpm_mphyc();
cpm_mphyc |= 0x3<<22;
write_cpm_mphyc(cpm_mphyc);
/* reset phy */
cpm_mphyc = read_cpm_mphyc();
cpm_mphyc_rst = cpm_mphyc & (1 << 24);
cpm_mphyc &= ~0x8;
cpm_mphyc |= 0x8;
write_cpm_mphyc(cpm_mphyc);
mdelay(1);
cpm_mphyc = read_cpm_mphyc();
cpm_mphyc &= ~0x8;
write_cpm_mphyc(cpm_mphyc);

/* */
status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase, 0x0, 0x18, &data);
if(status){
printf("GMAC read phy failed\n");
return 1;
}

/*printf("-- PHY power reset; 0x%04x\n", data);*/
data |= 1<<1;

status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase, 0x0, 0x18, data);

status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase, 0x0, 0x18, &data);
if(status){
printf("GMAC read phy failed\n");
return 1;
}
/*printf("++ PHY power reset; 0x%04x\n", data);*/

cpm_mphyc = read_cpm_mphyc();
cpm_mphyc_rst = cpm_mphyc & (1 << 24);
cpm_mphyc &= ~0x8;
cpm_mphyc |= 0x8;
write_cpm_mphyc(cpm_mphyc);
mdelay(1);
cpm_mphyc = read_cpm_mphyc();
cpm_mphyc &= ~0x8;
write_cpm_mphyc(cpm_mphyc);

/* wait for resetting successfully */
mdelay(1);
while(retry_cnt--){
cpm_mphyc = read_cpm_mphyc();
if((cpm_mphyc & (1 << 24)) ^ cpm_mphyc_rst)
break;
mdelay(1);
}
printf("cpm_mphyc_rst = 0x%08x cpm_mphyc = 0x%08x\n", cpm_mphyc_rst, cpm_mphyc & (1 << 24));
if(retry_cnt <= 0){
printf("====>GMAC failed to reset!\n");
}
}
#endif /* CONFIG_NET_PHY_TYPE */

#if defined (CONFIG_T15)
/* initialize t15 gmac gpio */
gpio_set_func(GPIO_PORT_B, GPIO_FUNC_0, 0xFFEFFFC0);
gpio_set_func(GPIO_PORT_E, GPIO_FUNC_0, 3<<12); //new gmac GPIO(MT10_core_20140904_v1_hefei.bin)
#elif defined (CONFIG_T10) || defined (CONFIG_T20) || defined (CONFIG_T30) || defined (CONFIG_T21)
/* initialize t10 gmac gpio */
#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_OMNI)
#else
gpio_set_func(GPIO_PORT_B, GPIO_FUNC_0, 0x1EFC0);
#endif
#endif

#else /* CONFIG_FPGA */

#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_DM9161)
/* reset PE10 */
gpio_direction_output(CONFIG_GPIO_DM9161_RESET, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
udelay(10);

gpio_direction_output(32*4+13, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
#if (CONFIG_NET_GMAC_PHY_MODE == GMAC_PHY_MII)
gpio_direction_output(32*1+13, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
#elif(CONFIG_NET_GMAC_PHY_MODE == GMAC_PHY_RMII)
gpio_direction_output(32*1+13, !CONFIG_GPIO_DM9161_RESET_ENLEVEL);
#endif /* CONFIG_NET_GMAC_PHY_MODE */
gpio_direction_output(32*1+10, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+15, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+24, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+25, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+26, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+27, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+6, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(32*1+8, !CONFIG_GPIO_DM9161_RESET_ENLEVEL);
gpio_direction_output(CONFIG_GPIO_DM9161_RESET, !CONFIG_GPIO_DM9161_RESET_ENLEVEL);
udelay(10);
#elif (CONFIG_NET_PHY_TYPE == PHY_TYPE_88E1111)
/* reset PE10 */
gpio_direction_output(CONFIG_GPIO_DM9161_RESET, CONFIG_GPIO_DM9161_RESET_ENLEVEL);
udelay(10);
gpio_direction_output(CONFIG_GPIO_DM9161_RESET, !CONFIG_GPIO_DM9161_RESET_ENLEVEL);
udelay(10);

#endif /* CONFIG_NET_PHY_TYPE */
gpio_set_func(GPIO_PORT_B, GPIO_FUNC_0, 0xFFFFFFC0);
gpio_set_func(GPIO_PORT_E, GPIO_FUNC_0, 3<<12); //new gmac GPIO(MT10_core_20140904_v1_hefei.bin)
#endif /* CONFIG_FPGA */


#if (CONFIG_NET_PHY_TYPE == PHY_TYPE_88E1111)

int phy_id;
u16 data;
s32 status = -ESYNOPGMACNOERR;
#if (CONFIG_NET_GMAC_PHY_MODE == GMAC_PHY_RGMII)

phy_id = check_phy_config(gmacdev);
Expand Down Expand Up @@ -661,6 +827,11 @@ int jz_net_initialize(bd_t *bis)
cpm_mphyc &= ~0x7;
cpm_mphyc |= 0x1;
write_cpm_mphyc(cpm_mphyc);
#elif (CONFIG_NET_GMAC_PHY_MODE == GMAC_PHY_MII)
cpm_mphyc = read_cpm_mphyc();
cpm_mphyc &= ~0x7;
cpm_mphyc |= 0x000;
write_cpm_mphyc(cpm_mphyc);
#endif //CONFIG_NET_GMAC_PHY_MODE

return phy_id;
Expand Down

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