Use Yosys Rosette backend

Dockerfile

@@ -166,15 +166,15 @@ RUN cd /root \
 # TODO(@cknizek?): Replace this with archive download
 # Yosys depends on a submodule (abc) and so downloading an archive doesn't work.
 # Once this issue (https://github.com/dear-github/dear-github/issues/214)...
-# ... is resolved, we can go back to downloading an archive.
-&& git clone https://github.com/YosysHQ/yosys.git \
-&& cd yosys \
-&& source /root/dependencies.sh \
-&& git checkout $YOSYS_COMMIT_HASH \
-&& git submodule update --init --recursive \
-&& PREFIX="/root/.local" CPLUS_INCLUDE_PATH="/usr/include/tcl8.6/:$CPLUS_INCLUDE_PATH" make config-gcc \
-&& PREFIX="/root/.local" CPLUS_INCLUDE_PATH="/usr/include/tcl8.6/:$CPLUS_INCLUDE_PATH" make -j ${MAKE_JOBS} install \
-&& rm -rf /root/yosys
+  # ... is resolved, we can go back to downloading an archive.
+  && source /root/dependencies.sh \
+  && git clone "$YOSYS_URL" \
+  && cd yosys \
+  && git checkout $YOSYS_COMMIT_HASH \
+  && git submodule update --init --recursive \
+  && PREFIX="/root/.local" CPLUS_INCLUDE_PATH="/usr/include/tcl8.6/:$CPLUS_INCLUDE_PATH" make config-gcc \
+  && PREFIX="/root/.local" CPLUS_INCLUDE_PATH="/usr/include/tcl8.6/:$CPLUS_INCLUDE_PATH" make -j ${MAKE_JOBS} install \
+  && rm -rf /root/yosys
 
 # Build CVC5.
 RUN source /root/dependencies.sh \

architecture_descriptions/intel_cyclone10lp.yml

@@ -1,9 +1,4 @@
 # Architecture description for Intel Cyclone 10 LP.
-#
-# This replaces the old intel.yml 
-# generic-ish altmult_accum block found in Quartus. It's unclear what
-# architecture this is actually for. We are adding support for a specific Intel
-# architecture (Cyclone 10 LP) instead.
 implementations:
   # TODO(@gussmith23): support optional parameters like c-width/d-width in this case.
   - interface: { name: DSP, parameters: { out-width: 36, a-width: 18, b-width: 18, c-width: 1, d-width: 1 } }

architecture_descriptions/xilinx_ultrascale_plus.yml

@@ -1,18 +1,18 @@
 implementations:
-  - interface: { name: LUT, parameters: { num_inputs: 2 } }
-    modules:
-      - module_name: LUT2
-        instance_name: LUT2
-        filepath: ../verilog/simulation/xilinx-ultrascale-plus/LUT2.v
-        parameters: [{ name: INIT, value: INIT }]
-        ports:
-          [
-            { name: I0, direction: input, bitwidth: 1, value: I0 },
-            { name: I1, direction: input, bitwidth: 1, value: I1 },
-            { name: O, direction: output, bitwidth: 1, value: O },
-          ]
-    internal_data: { INIT: 4 }
-    outputs: { O: (get LUT2 O) }
+  # - interface: { name: LUT, parameters: { num_inputs: 2 } }
+  #   modules:
+  #     - module_name: LUT2
+  #       instance_name: LUT2
+  #       filepath: ../verilog/simulation/xilinx-ultrascale-plus/LUT2.v
+  #       parameters: [{ name: INIT, value: INIT }]
+  #       ports:
+  #         [
+  #           { name: I0, direction: input, bitwidth: 1, value: I0 },
+  #           { name: I1, direction: input, bitwidth: 1, value: I1 },
+  #           { name: O, direction: output, bitwidth: 1, value: O },
+  #         ]
+  #   internal_data: { INIT: 4 }
+  #   outputs: { O: (get LUT2 O) }
   - interface: { name: LUT, parameters: { num_inputs: 6 } }
     modules:
       - module_name: LUT6