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Fix module names in export of verilog testbenches #1288

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Fix module names in export of verilog testbenches #1288

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59393e0
Fix module names in verilog testbenches
olofos May 1, 2024
ef3138a
Add tests for verilog test bench generator
olofos May 1, 2024
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5 changes: 3 additions & 2 deletions src/main/java/de/neemann/digital/hdl/verilog2/VerilogGenerator.java
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Original file line number Diff line number Diff line change
Expand Up @@ -87,9 +87,10 @@ public VerilogGenerator export(Circuit circuit) throws IOException {
String fileName = out.getFile() != null ? out.getFile().getName() : circuit.getOrigin().getName();
String[] tokens = fileName.split("(?=(\\.[^\\.]+)$)"); // The power of regex :)

String topModuleName = vrename.checkName(tokens[0]);
String topModuleName = tokens[0];
String checkedTopModuleName = vrename.checkName(topModuleName);

new VerilogCreator(out, library).printHDLCircuit(model.getMain(), topModuleName, model.getRoot());
new VerilogCreator(out, library).printHDLCircuit(model.getMain(), checkedTopModuleName, model.getRoot());

File outFile = out.getFile();
if (outFile != null) {
Expand Down
7 changes: 5 additions & 2 deletions src/main/java/de/neemann/digital/hdl/verilog2/VerilogTestBenchCreator.java
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Expand Up @@ -105,9 +105,11 @@ public ArrayList<File> getTestFileWritten() {
}

private void writeTestBench(CodePrinter out, String moduleName, String testName, Circuit.TestCase tc) throws IOException, HDLException, TestingDataException, ParserException {
HDLModel.Renaming vrename = new VerilogRenaming();

out.print("// A testbench for ").println(testName);
out.println("`timescale 1us/1ns").println();
out.print("module ").print(testName).println(";");
out.print("module ").print(vrename.checkName(testName)).println(";");

// Write local port declaration
out.inc();
Expand All @@ -117,7 +119,8 @@ private void writeTestBench(CodePrinter out, String moduleName, String testName,
}

out.println();
out.print(moduleName).print(" ").print(moduleName).print("0 (").println();
out.print(vrename.checkName(moduleName)).print(" ").print(vrename.checkName(moduleName + "0")).print(" (")
.println();
out.inc();

Separator comma = new Separator(out, ",\n");
Expand Down
69 changes: 69 additions & 0 deletions src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java
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Expand Up @@ -6,9 +6,18 @@
package de.neemann.digital.hdl.verilog2;

import de.neemann.digital.hdl.printer.CodePrinterStr;
import de.neemann.digital.core.extern.ProcessStarter;
import de.neemann.digital.hdl.printer.CodePrinter;
import de.neemann.digital.integration.ToBreakRunner;
import junit.framework.TestCase;

import java.io.File;
import java.nio.file.Files;
import java.text.DateFormat;
import java.text.SimpleDateFormat;
import java.util.ArrayList;
import java.util.Date;

public class VerilogGeneratorTest extends TestCase {

public void testComb() throws Exception {
Expand Down Expand Up @@ -202,4 +211,64 @@ public void testNames() throws Exception {
"endmodule\n", out.toString());
}

public void testTestCaseNames() throws Exception {
DateFormat f = new SimpleDateFormat("yy-MM-dd_HH-mm_ss");
String time = f.format(new Date());

ToBreakRunner br = new ToBreakRunner("dig/hdl_names/a-b.dig");
File dir = Files.createTempDirectory("digital_verilog_testcase_" + time + "_").toFile();
File srcFile = new File(dir, "a-b.dig");
CodePrinter out = new CodePrinter(srcFile);
VerilogGenerator generator = new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
ArrayList<File> testbenches = generator.getTestBenches();
assertEquals(testbenches.size(), 1);

File test_file = testbenches.get(0);
assertEquals(test_file.getName(), "a-b_tb.v");

assertEquals("// A testbench for a-b_tb\n" +
"`timescale 1us/1ns\n" +
"\n" +
"module \\a-b_tb ;\n" +
" reg A;\n" +
" reg B;\n" +
" wire Y;\n" +
"\n" +
" \\a-b \\a-b0 (\n" +
" .A(A),\n" +
" .B(B),\n" +
" .Y(Y)\n" +
" );\n" +
"\n" +
" reg [2:0] patterns[0:3];\n" +
" integer i;\n" +
"\n" +
" initial begin\n" +
" patterns[0] = 3'b0_0_0;\n" +
" patterns[1] = 3'b0_1_0;\n" +
" patterns[2] = 3'b1_0_0;\n" +
" patterns[3] = 3'b1_1_1;\n" +
"\n" +
" for (i = 0; i < 4; i = i + 1)\n" +
" begin\n" +
" A = patterns[i][2];\n" +
" B = patterns[i][1];\n" +
" #10;\n" +
" if (patterns[i][0] !== 1'hx)\n" +
" begin\n" +
" if (Y !== patterns[i][0])\n" +
" begin\n" +
" $display(\"%d:Y: (assertion error). Expected %h, found %h\", i, patterns[i][0], Y);\n" +
" $finish;\n" +
" end\n" +
" end\n" +
" end\n" +
"\n" +
" $display(\"All tests passed.\");\n" +
" end\n" +
" endmodule\n",
new String(Files.readAllBytes(test_file.toPath())));

ProcessStarter.removeFolder(dir);
}
}
10 changes: 10 additions & 0 deletions src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
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Expand Up @@ -69,6 +69,16 @@ public void testInSimulator2() throws Exception {
}
}

public void testInSimulatorNames() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/hdl_names");
try {
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
assertEquals(3, tested);
} catch (FileScanner.SkipAllException e) {
// if iverilog is not installed its also ok
}
}

public void testInSimulatorInOut() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test/pinControl");
try {
Expand Down
74 changes: 74 additions & 0 deletions src/test/resources/dig/hdl_names/a-b.dig
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Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>2</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>And</elementName>
<elementAttributes/>
<pos x="380" y="200"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Y</string>
</entry>
</elementAttributes>
<pos x="460" y="220"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>A</string>
</entry>
</elementAttributes>
<pos x="360" y="200"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>B</string>
</entry>
</elementAttributes>
<pos x="360" y="240"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
<elementAttributes>
<entry>
<string>Testdata</string>
<testData>
<dataString>A B Y
0 0 0
0 1 0
1 0 0
1 1 1
</dataString>
</testData>
</entry>
</elementAttributes>
<pos x="320" y="100"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="360" y="240"/>
<p2 x="380" y="240"/>
</wire>
<wire>
<p1 x="360" y="200"/>
<p2 x="380" y="200"/>
</wire>
<wire>
<p1 x="440" y="220"/>
<p2 x="460" y="220"/>
</wire>
</wires>
<measurementOrdering/>
</circuit>