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JosephAbbey committed Jun 24, 2023
1 parent f71ceb7 commit 47f7cc2
Showing 1 changed file with 15 additions and 5 deletions.
20 changes: 15 additions & 5 deletions design/design_entry.vhdl.sbe
Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,19 @@
"stop": "buttons(1)"
},
"signals": {
"start_r": "std_logic",
"stop_r": "std_logic",
"state": "natural range 0 to 7"
"start_r": [
"std_logic",
"'0'"
],
"stop_r": [
"std_logic",
"'0'"
],
"state": [
"natural range 0 to 7",
"(others => '0')"
]
},
"command": "../design/modelsim_compile.cmd design_entry.vhdl"
}
"command": "../design/modelsim_compile.cmd design_entry.vhdl",
"libraries": {}
}

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