Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)

Name		Name	Last commit message	Last commit date
Latest commit History 295 Commits
fpga		fpga
hello_world		hello_world
media		media
scripts		scripts
sim-unisim		sim-unisim
tests		tests
.gitignore		.gitignore
.travis.yml		.travis.yml
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
cache_ram.vhdl		cache_ram.vhdl
common.vhdl		common.vhdl
control.vhdl		control.vhdl
core.vhdl		core.vhdl
core_debug.vhdl		core_debug.vhdl
core_tb.vhdl		core_tb.vhdl
countzero.vhdl		countzero.vhdl
countzero_tb.vhdl		countzero_tb.vhdl
cr_file.vhdl		cr_file.vhdl
cr_hazard.vhdl		cr_hazard.vhdl
crhelpers.vhdl		crhelpers.vhdl
decode1.vhdl		decode1.vhdl
decode2.vhdl		decode2.vhdl
decode_types.vhdl		decode_types.vhdl
divider.vhdl		divider.vhdl
divider_tb.vhdl		divider_tb.vhdl
dmi_dtm_dummy.vhdl		dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl		dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl		dmi_dtm_xilinx.vhdl
execute1.vhdl		execute1.vhdl
fetch1.vhdl		fetch1.vhdl
fetch2.vhdl		fetch2.vhdl
glibc_random.vhdl		glibc_random.vhdl
glibc_random_helpers.vhdl		glibc_random_helpers.vhdl
gpr_hazard.vhdl		gpr_hazard.vhdl
helpers.vhdl		helpers.vhdl
icache.vhdl		icache.vhdl
icache_tb.vhdl		icache_tb.vhdl
icache_test.bin		icache_test.bin
insn_helpers.vhdl		insn_helpers.vhdl
loadstore1.vhdl		loadstore1.vhdl
loadstore2.vhdl		loadstore2.vhdl
logical.vhdl		logical.vhdl
microwatt.core		microwatt.core
multiply.vhdl		multiply.vhdl
multiply_tb.vhdl		multiply_tb.vhdl
plru.vhdl		plru.vhdl
plru_tb.vhdl		plru_tb.vhdl
ppc_fx_insns.vhdl		ppc_fx_insns.vhdl
register_file.vhdl		register_file.vhdl
rotator.vhdl		rotator.vhdl
rotator_tb.vhdl		rotator_tb.vhdl
sim_console.vhdl		sim_console.vhdl
sim_console_c.c		sim_console_c.c
sim_jtag.vhdl		sim_jtag.vhdl
sim_jtag_socket.vhdl		sim_jtag_socket.vhdl
sim_jtag_socket_c.c		sim_jtag_socket_c.c
sim_uart.vhdl		sim_uart.vhdl
simple_ram_behavioural.vhdl		simple_ram_behavioural.vhdl
simple_ram_behavioural_helpers.vhdl		simple_ram_behavioural_helpers.vhdl
simple_ram_behavioural_helpers_c.c		simple_ram_behavioural_helpers_c.c
simple_ram_behavioural_tb.bin		simple_ram_behavioural_tb.bin
simple_ram_behavioural_tb.vhdl		simple_ram_behavioural_tb.vhdl
soc.vhdl		soc.vhdl
wishbone_arbiter.vhdl		wishbone_arbiter.vhdl
wishbone_debug_master.vhdl		wishbone_debug_master.vhdl
wishbone_types.vhdl		wishbone_types.vhdl
writeback.vhdl		writeback.vhdl

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