Improve Testing and Harden Digital Downconverter

[google-labs-jules]

This change introduces a new test suite for edge cases in the digital_downconverter.py module, uncovering and fixing two bugs related to zero-bandwidth configurations and non-complex input types. The test suite has been enhanced to be more robust, and the core DDC code is now hardened against invalid inputs. Additionally, the project's .gitignore has been updated to exclude build artifacts.

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PR created automatically by Jules for task 12166722648448870325 started by @iamdarshg

[google-labs-jules]

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[iamdarshg]

This is good, but I need testing for more than just the fft. Modify all tests to test the verilog in the intended manner. Feel free to rewrite the whole verilog testing regime since it wasn't built with very good or honestly any understanding of what's going on.

[google-labs-jules]

This is good, but I need testing for more than just the fft. Modify all tests to test the verilog in the intended manner. Feel free to rewrite the whole verilog testing regime since it wasn't built with very good or honestly any understanding of what's going on.

Understood. I will rewrite the Verilog testing regime to be more comprehensive and to properly test the Verilog modules. I will create a new plan to address this and begin working on it right away.

[iamdarshg]

Observations and action items for Verilog tests related to the Digital Downconverter (DDC)

Summary

• The repo has test orchestration (tests/scripts/run_all_tests.sh) and Verilog testbenches (verilog/digital_downconverter_tb.v), but the current test infra is brittle and DDC coverage is not guaranteed in CI.
• There are three classes of issues blocking reliable DDC testing:

1. Python/cocotb environment/plugin issues (pytest plugin missing -> cocotb tests fail).
2. Test selection logic in the runner expects cocotb tests for every module and doesn't reliably fallback to Verilog TBs.
3. Loss of previously-stored performance artifacts (json/png) and no automated performance postprocessing.

Immediate recommendations (actionable)

• Fix test environment dependencies

1. Add the correct Python packages to tests/requirements.txt, e.g.:
   cocotb
   pytest
   pytest-cocotb (or the correct plugin name used by run_all_tests.sh)
   cocotb-tools (if your runner expects it)
2. Confirm the exact plugin name used by pytest invocation (run_all_tests.sh uses -p pytest_cocotb). Make the invocation and requirements aligned.
3. Ensure DDC tests run deterministically in CI Option A (preferred): Add a cocotb test for the DDC:
   tests/cocotb_tests/test_digital_downconverter.py
   The test should be self-checking: drive adc_data, nco values and assert expected I/Q outputs and output_valid.
   Keep test runtime bounded (add cycle/timeouts) and deterministic stimulus. Option B: Improve run_all_tests.sh fallback:
   If no cocotb test exists, automatically compile and run verilog/digital_downconverter_tb.v with Verilator/iverilog and treat non-zero exit or missing expected prints as failure.

• Make Verilog TBs Verilator-friendly and faster

1. Verify timescale is present (timescale 1ns/1ps) and matches simulator expectations.
2. Avoid constructs that cause Verilator compile/runtime errors:
   - procedural ROM initialization with $rtoi/$sin/$cos needs pre-computed constants or compatible initialization. (nco_generator ROM earlier had a fix — confirm similar patterns in DDC submodules.)
   - initial blocks that use non-blocking <= in testbench initialization can cause issues; use blocking = assignments in initial blocks where appropriate.
3. Reduce timeouts: very long timeouts in TBs slow CI drastically. Use reasonable simulation timeouts and fail fast with helpful state dumps.

• Restore automated performance capture

1. Add a small post-processing script (tools/collect_performance.py) that:
   parses cocotb logs,
   extracts latency/throughput metrics,
   writes JSON/CSV (e.g. tests/perf/YYYYMMDD_ddc_performance.json)
   generates plots (PNG) if desired.
2. Update CI to upload these files as job artifacts (do not commit large generated artifacts to the repo).

Acceptance criteria

1. The DDC has either a passing cocotb test or the Verilog TB is exercised and exits successfully in CI.
   - CI installs tests/requirements.txt and the pytest/cocotb plugin used by run_all_tests.sh.
   - Performance JSON is produced when the tests run and uploaded as a CI artifact.

[iamdarshg]

Closed on account of jules giving up.