Overhaul Verilog Test Infrastructure with Cocotb#9
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This commit replaces the entire Verilog test infrastructure with a new suite of `cocotb` tests. The old, brittle testbenches have been removed and replaced with a modern, Python-based framework that uses Verilator for simulation. The new test suite includes: - Unit tests for `adc_interface`, `digital_downconverter`, `fft_processor`, `ethernet_mac`, and `udp_ip_stack`. - A top-level integration test for the `fpga_processing_pipeline` to verify the entire data flow. - An updated `run_all_tests.sh` script to execute the new test suite. - Updated documentation in `tests/README.md`. NOTE: Due to persistent issues with the test runner's virtual environment setup, the tests have not been successfully run. The submission is being made at the user's request.
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This submission introduces a completely new
cocotb-based test suite for the Verilog modules, replacing the old, brittle infrastructure. It includes unit tests for core modules, a top-level integration test, and an updated test runner. Please note that the tests have not been successfully run due to environment setup issues.PR created automatically by Jules for task 6873724901403234441 started by @iamdarshg