Synchronizes the de-assertion of asynchronous reset to the design's clock domain.
Source file: areset_sync.sv
Synchronizes both the assertion & de-assertion of an asynchronous reset and generates a fully synchronous reset to the design's clock domain. This suitable for FPGA designs.
Source file: reset_sync.sv
Synchronizes 1-bit signal from source clock domain safely to destination clock domain.
Source files:
cdc_sync.sv -- without reset
cdc_sync_with_sync.sv -- with async reset
cdc_sync_with_rst.sv -- with fully sync reset (suitable for FPGAs)
All codes are fully synthesizable and tested. All are open-source codes, free to use, modify and distribute without any conflicts of interest with the original developer.
Mitu Raj, iammituraj@gmail.com, chip@chipmunklogic.com