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[ESIMD][NFC] Rework L1/L2 cache hints passing across internal funcs(p… #12935

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Mar 7, 2024
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[ESIMD][NFC] Rework L1/L2 cache hints passing across internal funcs(p… #12935

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4 changes: 0 additions & 4 deletions llvm/lib/SYCLLowerIR/ESIMD/LowerESIMD.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -512,10 +512,6 @@ class ESIMDIntrinDescTable {
{"lsc.load.merge.bti",
{ai1(0), c8(lsc_subopcode::load), t8(1), t8(2), t16(3), t32(4), t8(5),
t8(6), t8(7), c8(0), a(1), aSI(2), a(3)}}},
{"lsc_load_stateless",
{"lsc.load.stateless",
{ai1(0), c8(lsc_subopcode::load), t8(1), t8(2), t16(3), t32(4), t8(5),
t8(6), t8(7), c8(0), a(1), c32(0)}}},
{"lsc_load_merge_stateless",
{"lsc.load.merge.stateless",
{ai1(0), c8(lsc_subopcode::load), t8(1), t8(2), t16(3), t32(4), t8(5),
Expand Down
43 changes: 19 additions & 24 deletions sycl/include/sycl/ext/intel/esimd/common.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -551,10 +551,25 @@ constexpr bool are_both(cache_hint First, cache_hint Second, cache_hint Val) {

enum class cache_action { prefetch, load, store, atomic };

template <cache_action Action, cache_hint L1Hint, cache_hint L2Hint>
void check_cache_hint() {
constexpr auto L1H = cache_hint_wrap<L1Hint>{};
constexpr auto L2H = cache_hint_wrap<L2Hint>{};
template <typename PropertyListT> constexpr bool has_cache_hints() {
constexpr cache_hint L1H =
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
constexpr cache_hint L2H =
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
return L1H != cache_hint::none || L2H != cache_hint::none;
}

// Currently, this is just a wrapper around 'check_cache_hint' function.
// It accepts the compile-time properties that may include cache-hints
// to be verified.
template <cache_action Action, typename PropertyListT>
void check_cache_hints() {
constexpr auto L1H =
cache_hint_wrap<getPropertyValue<PropertyListT, cache_hint_L1_key>(
cache_hint::none)>{};
constexpr auto L2H =
cache_hint_wrap<getPropertyValue<PropertyListT, cache_hint_L2_key>(
cache_hint::none)>{};
if constexpr (Action == cache_action::prefetch) {
static_assert(
L1H.template is_one_of<cache_hint::cached, cache_hint::uncached,
Expand Down Expand Up @@ -590,26 +605,6 @@ void check_cache_hint() {
}
}

template <typename PropertyListT> constexpr bool has_cache_hints() {
constexpr cache_hint L1H =
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
constexpr cache_hint L2H =
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
return L1H != cache_hint::none || L2H != cache_hint::none;
}

// Currently, this is just a wrapper around 'check_cache_hint' function.
// It accepts the compile-time properties that may include cache-hints
// to be verified.
template <cache_action Action, typename PropertyListT>
void check_cache_hints() {
constexpr cache_hint L1H =
getPropertyValue<PropertyListT, cache_hint_L1_key>(cache_hint::none);
constexpr cache_hint L2H =
getPropertyValue<PropertyListT, cache_hint_L2_key>(cache_hint::none);
check_cache_hint<Action, L1H, L2H>();
}

constexpr lsc_data_size expand_data_size(lsc_data_size DS) {
if (DS == lsc_data_size::u8)
return lsc_data_size::u8u32;
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27 changes: 0 additions & 27 deletions sycl/include/sycl/ext/intel/esimd/detail/memory_intrin.hpp
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Expand Up @@ -831,33 +831,6 @@ __esimd_lsc_load_merge_stateless(
__ESIMD_DNS::vector_type_t<Ty, N * __ESIMD_DNS::to_int<VS>()> pass_thru = 0)
__ESIMD_INTRIN_END;

/// USM pointer gather.
/// Supported platforms: DG2, PVC
///
/// Collects elements located at specified address and returns them
/// as a single \ref simd object.
///
/// @tparam Ty is element type.
/// @tparam L1H is L1 cache hint.
/// @tparam L2H is L2 cache hint.
/// @tparam AddressScale is the address scale.
/// @tparam ImmOffset is the immediate offset added to each address.
/// @tparam DS is the data size.
/// @tparam VS is the number of elements to load per address.
/// @tparam Transposed indicates if the data is transposed during the transfer.
/// @tparam N is the SIMD size of operation (the number of addresses to access)
/// @param pred is predicates.
/// @param addrs is the load addresses.
/// @return is a vector of type T and N * to_int<VS>()
template <typename Ty, __ESIMD_NS::cache_hint L1H, __ESIMD_NS::cache_hint L2H,
uint16_t AddressScale, int ImmOffset, __ESIMD_DNS::lsc_data_size DS,
__ESIMD_DNS::lsc_vector_size VS,
__ESIMD_DNS::lsc_data_order Transposed, int N>
__ESIMD_INTRIN __ESIMD_DNS::vector_type_t<Ty, N * __ESIMD_DNS::to_int<VS>()>
__esimd_lsc_load_stateless(__ESIMD_DNS::simd_mask_storage_t<N> pred,
__ESIMD_DNS::vector_type_t<uintptr_t, N> addrs)
__ESIMD_INTRIN_END;

/// USM pointer scatter.
/// Supported platforms: DG2, PVC
///
Expand Down
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