[SYCL][ESIMD] Replace use of intrinsics with spirv functions for addc/subb

[fineg74]

No description provided.

[v-klochkov]

let's keep the lowering in LowerESIMD.cpp for a while - see the reasoning in other PR: #12935

[fineg74]

Fixed

[v-klochkov]

I believe the help of a macro would make it better: a) there will be no need for SFINAE and b) the templates would not require extra parameter T, which goes in very unusual order - after N - (usual order is <T, N>). Finally, passing simd_view as the 1 arg to vector+scalar op will require specifying only N, instead of <N, T>.
The idea is: (it may need some adaptation because of using SYCL_DEVICE_ONLY inside it:

#define __ESIMD_ADDC(T) \
template <int N> \
__ESIMD_API __ESIMD_NS::simd<T, N>> \
addc(__ESIMD_NS::simd<T, N> &carry, __ESIMD_NS::simd<T, N> src0, \
     __ESIMD_NS::simd<T, N> src1) { \
#ifdef __SYCL_DEVICE_ONLY__ \
  std::pair<__ESIMD_DNS::vector_type_t<T, N>, __ESIMD_DNS::vector_type_t<T, N>> \
      Result = __spirv_IAddCarry<T, N>(src0.data(), src1.data()); \
  carry = Result.second; \
  return Result.first; \
#else \
  return 0; \
#endif // __SYCL_DEVICE_ONLY__ \
} \
/* OTHER 3 variants here (vec+scalar, scalar+vec, sccalar+scalar  */ \

__ESIMD_ADDC(uint8_t)
__ESIMD_ADDC(uint16_t)
__ESIMD_ADDC(uint32_t)
__ESIMD_ADDC(uint64_t)

[fineg74]

Done

[v-klochkov]

Please add 64-bit case too - it was the main inspiration/reason for support of ADDC/SUBB via SPIRV.

[fineg74]

Please add 64-bit case too - it was the main inspiration/reason for support of ADDC/SUBB via SPIRV.

Done

[sarnex]

lgtm!

[sarnex]

is this working now because we bumped the driver?

[fineg74]

Frankly speaking don't remember most likely I just added test cases. New driver was for handling 64 bit data

[sarnex]

sorry i meant the entire PR not this code specifically, my bad

[fineg74]

Yes entire PR waited for new driver. There was a delay since there was a bug discovered on GPU side after initial implementation. Once Windows driver get updated I will revisit it to see if it resolves the issue of test failures on Windows

[sarnex]

cool, thx

[fineg74]

@uditagarwal97, @intel/llvm-reviewers-runtime, Could you please review this PR

[uditagarwal97]

SYCL changes LGTM.

[fineg74]

@intel/llvm-gatekeepers, I believe the PR is ready to be merged.