Skip to content

Commit 42a4e90

Browse files
authored
Improve error messages for SSA checks (#625)
1 parent c904f46 commit 42a4e90

File tree

2 files changed

+64
-10
lines changed

2 files changed

+64
-10
lines changed

lib/src/modules/conditionals/conditional.dart

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -160,6 +160,12 @@ abstract class Conditional {
160160
continue;
161161
}
162162

163+
// if at this point there's still a srcConnection, then something is wrong
164+
// and someone probably reused a signal when they shouldn't have
165+
if (ssaDriver.srcConnection != null) {
166+
throw MappedSignalAlreadyAssignedException(ssaDriver.ref.name);
167+
}
168+
163169
ssaDriver <= mappings[ssaDriver.ref]!;
164170
}
165171
}

test/ssa_test.dart

Lines changed: 58 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -437,6 +437,47 @@ class SsaPipeJump extends Module {
437437
}
438438
}
439439

440+
class ProcessingModule extends Module {
441+
late final Logic x = addOutput('x_p', width: 8);
442+
late final Logic y = addOutput('y_p', width: 8);
443+
ProcessingModule(Logic a) : super(name: 'processing') {
444+
a = addInput('a_p', a, width: 8);
445+
446+
x <= a + 1;
447+
y <= a + 2;
448+
}
449+
}
450+
451+
class SsaMultiUseModule extends SsaTestModule {
452+
SsaMultiUseModule(Logic a, {bool badDoubleUse = true})
453+
: super(name: 'multi_use') {
454+
a = addInput('a', a, width: 8);
455+
addOutput('x', width: 8);
456+
final z = Logic(name: 'z', width: 8);
457+
458+
final s1 = Logic(name: 's1', width: 8);
459+
460+
Combinational.ssa((s) => [
461+
s(s1) < a,
462+
if (badDoubleUse)
463+
...() {
464+
final pmod = ProcessingModule(s(s1));
465+
return [
466+
If(pmod.y.lt(5), then: [s(z) < 1]),
467+
s(x) < pmod.x,
468+
];
469+
}()
470+
else ...[
471+
If(ProcessingModule(s(s1)).y.lt(5), then: [s(z) < 1]),
472+
s(x) < ProcessingModule(s(s1)).x,
473+
]
474+
]);
475+
}
476+
477+
@override
478+
int model(int a) => a + 1;
479+
}
480+
440481
void main() {
441482
tearDown(() async {
442483
await Simulator.reset();
@@ -456,18 +497,25 @@ void main() {
456497
SimCompare.checkIverilogVector(mod, vectors);
457498
});
458499

500+
test('ssa multi use model bad reuse', () {
501+
expect(() => SsaMultiUseModule(Logic(name: 'a', width: 8)),
502+
throwsA(isA<MappedSignalAlreadyAssignedException>()));
503+
});
504+
459505
group('ssa_test_module', () {
460-
final aInput = Logic(width: 8, name: 'a');
506+
Logic aInput() => Logic(width: 8, name: 'a');
507+
461508
final mods = [
462-
SsaModAssignsOnly(aInput),
463-
SsaModIf(aInput),
464-
SsaModCase(aInput),
465-
SsaChain(aInput),
466-
SsaMix(aInput),
467-
SsaNested(aInput),
468-
SsaMultiDep(aInput),
469-
SsaModWithStructElements(aInput),
470-
SsaModWithStructSplit(aInput),
509+
SsaModAssignsOnly(aInput()),
510+
SsaModIf(aInput()),
511+
SsaModCase(aInput()),
512+
SsaChain(aInput()),
513+
SsaMix(aInput()),
514+
SsaNested(aInput()),
515+
SsaMultiDep(aInput()),
516+
SsaModWithStructElements(aInput()),
517+
SsaModWithStructSplit(aInput()),
518+
SsaMultiUseModule(aInput(), badDoubleUse: false),
471519
];
472520

473521
for (final mod in mods) {

0 commit comments

Comments
 (0)