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Pull requests: intel/rohd

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Pull requests list

Mark bit ranges of swizzles with comments in generated SystemVerilog
#627 opened Oct 22, 2025 by mkorbel1 Loading…
1
Add LogicEnum for enumerable types as hardware signals
#599 opened Jun 25, 2025 by mkorbel1 • Draft
Add docs about trusting ROHD for development
#589 opened Mar 18, 2025 by mkorbel1 Loading…
SystemVerilog block labels
#585 opened Mar 8, 2025 by lucasphillips Loading…
1
21
Avoid Module creation for Constant Gate scenarios
#481 opened Apr 5, 2024 by mjayasim9 Loading…
1
10
Vscode extension
#437 opened Nov 14, 2023 by quekyj Loading…
18
[WIP] Add local Markdown checks
#330 opened Mar 22, 2023 by chykon • Draft
Automatically check for new Dart lints
#284 opened Feb 24, 2023 by chykon • Draft
2
Fix bug related to clock divider simulation, fix #191
#192 opened Nov 1, 2022 by mkorbel1 • Draft
1
3
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