Sequential outputs as clock inputs to other Sequentials trigger late in the simulator #191
Description
Describe the bug
If the output of one Sequential is used as a clock trigger to another Sequential, the phased simulator can sometimes detect the edge and drive the outputs of the downstream Sequential one tick late.
This breaks clock dividers.
To Reproduce
Create a clock divider and connect a flop to the output of the divided clock.
Expected behavior
Divided clock properly triggers edge detection on Sequentials.
Actual behavior
Divided clock doesn't trigger edges properly, causing incorrect Sequential behavior.
Additional: Dart SDK info
No response
Additional: pubspec.yaml
No response
Additional: Context
No response