Elements

[eulere28]

Hi all.
I have one question on the elements,

For example, I initialized the addR as 1 first as the elements['int'] only accept integer.

If I didn't do so, it will get error like this:

So, It is possible to not to initialize the value for addR (hence the elements accept an unknown variable) and the generated verilog code will be (readData < memory[addR]) but not (readData < memory[1(initialized value)]).

Thanks.

[mkorbel1]

Hi @eulere28, thanks for the question!

You cannot use a Logic to access the index of an array (currently) in ROHD. One way to achieve this is the way that is done in the ROHD-HCL register file:
https://github.com/intel/rohd-hcl/blob/main/lib/src/memory/register_file.dart

Effectively, when you do an index operation like that in SystemVerilog, there's hardware implied to do the selection operation. ROHD currently requires you to be more explicit.

Soon, the resolution of this issue will make this type of thing easier to implement: #116
Soon, this will also help with array assignment: #377

Does that answer your question?