[LLVMGPU] Enable scf.forall distr. on vectorDistribute Pipeline #19420
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Max191
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Jan 10, 2025
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| // CHECK-DAG: %[[LHS_RD:.+]] = vector.transfer_read %[[B0]]{{.*}} vector<1xf16> | ||
| // CHECK-DAG: vector.transfer_write %[[LHS_RD]] | ||
| // Note that to simplify the test we are not showing the mapping of the RHS_RD | ||
| // to its buffer as it goes through an scf.if/else control structure | ||
| // involving allocas. | ||
| // CHECK-DAG: %[[RHS_RD:.+]] = vector.transfer_read {{.*}} vector<1xf16> | ||
| // CHECK-DAG: vector.transfer_write %[[RHS_RD]] |
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What happened to these reads?
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These happen if the tensor.extract_slices are pushed up in the block. Buffer optimization is kicking in.
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| // CHECK-DAG: %[[LHS_RD:.+]] = vector.transfer_read {{.*}} vector<4xf32> | ||
| // CHECK-DAG: vector.transfer_write %[[LHS_RD]] | ||
| // CHECK-DAG: %[[RHS_RD:.+]] = vector.transfer_read {{.*}} vector<1xf32> | ||
| // CHECK-DAG: vector.transfer_write %[[RHS_RD]] |
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| // CHECK-SAME: -> (vector<1x1x1xf32>, vector<1x1x1xf32>, vector<1x2x1x4x1x4xf32>) | ||
| // CHECK-COUNT-24: amdgpu.mfma {{.*}} {blocks = 1 : i32, k = 8 : i32, m = 32 : i32, n = 32 : i32} blgp = none : vector<4xf16>, vector<4xf16>, vector<16xf32> |
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Why has the number of mfmas changed here?
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The distribution now happens on tile sizes of any length (previously, it was limited to 3). That's why there is a change in count.
Max191
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Enables
scf.foralldistribution on the vector distribute pipeline.