Final project for the course "Reti Logiche" held at Politecnico di Milano (2022/23).
Final vote: 30/30
Language: VHDL
Software used: Vivado
Project by Matteo Lussana (@matteo-lussana) and Irene Lo Presti (@irelop).
Implementation of a HW module that interfaces with RAM memory and that follows the indications given in the requirements.
The system receives information about a memory location whose content must be directed towards one of four available output channels. Indications are provided via a one-bit serial input, while the system outputs provide all bits of the memory word in parallel.
The specific requirements (written in Italian) here.
The diagrams of the state machine and the datapath are available in the report.