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# Conflicts:
#	codeGenCpu6502/src/prog8/codegen/cpu6502/IfElseAsmGen.kt
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@irmen
irmen committed Nov 8, 2024
2 parents 4152f7e + 688dce6 commit 50343a1
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Showing 53 changed files with 606 additions and 592 deletions.
6 changes: 4 additions & 2 deletions .gitignore
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Original file line number Diff line number Diff line change
@@ -1,9 +1,12 @@
.idea/workspace.xml
.idea/discord.xml
.idea/developer-tools.xml
.idea/usage.statistics.xml
.idea/shelf/
build/
dist/
output/
out/
.*cache/
*.directory
*.prg
Expand All @@ -12,7 +15,6 @@ output/
*.vm.txt
*.vice-mon-list
docs/build
out/
parser/**/*.interp
parser/**/*.tokens
parser/**/*.java
Expand All @@ -23,6 +25,7 @@ compiler/src/prog8/buildversion/*
.eggs/
/MANIFEST
.tox/
.kotlin/
__pycache__/
parser.out
parsetab.py
Expand All @@ -31,7 +34,6 @@ parsetab.py
compiler/lib/

.gradle
/prog8compiler.jar
sd*.img
*.d64

14 changes: 7 additions & 7 deletions codeCore/src/prog8/code/SymbolTable.kt
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Expand Up @@ -98,7 +98,7 @@ enum class StNodeType {
// MODULE, // not used with current scoping rules
BLOCK,
SUBROUTINE,
ROMSUB,
EXTSUB,
LABEL,
STATICVAR,
MEMVAR,
Expand Down Expand Up @@ -257,17 +257,17 @@ class StSub(name: String, val parameters: List<StSubroutineParameter>, val retur
StNode(name, StNodeType.SUBROUTINE, astNode)


class StRomSub(name: String,
val address: PtAsmSub.Address?, // null in case of asmsub, specified in case of romsub.
val parameters: List<StRomSubParameter>,
val returns: List<StRomSubParameter>,
class StExtSub(name: String,
val address: PtAsmSub.Address?, // null in case of asmsub, specified in case of extsub.
val parameters: List<StExtSubParameter>,
val returns: List<StExtSubParameter>,
astNode: PtNode) :
StNode(name, StNodeType.ROMSUB, astNode)
StNode(name, StNodeType.EXTSUB, astNode)



class StSubroutineParameter(val name: String, val type: DataType)
class StRomSubParameter(val register: RegisterOrStatusflag, val type: DataType)
class StExtSubParameter(val register: RegisterOrStatusflag, val type: DataType)
class StArrayElement(val number: Double?, val addressOfSymbol: String?, val boolean: Boolean?) {
init {
if(number!=null) require(addressOfSymbol==null && boolean==null)
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6 changes: 3 additions & 3 deletions codeCore/src/prog8/code/SymbolTableMaker.kt
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Expand Up @@ -39,9 +39,9 @@ class SymbolTableMaker(private val program: PtProgram, private val options: Comp
private fun addToSt(node: PtNode, scope: ArrayDeque<StNode>) {
val stNode = when(node) {
is PtAsmSub -> {
val parameters = node.parameters.map { StRomSubParameter(it.first, it.second.type) }
val returns = node.returns.map { StRomSubParameter(it.first, it.second) }
StRomSub(node.name, node.address, parameters, returns, node)
val parameters = node.parameters.map { StExtSubParameter(it.first, it.second.type) }
val returns = node.returns.map { StExtSubParameter(it.first, it.second) }
StExtSub(node.name, node.address, parameters, returns, node)
}
is PtBlock -> {
StNode(node.name, StNodeType.BLOCK, node)
Expand Down
2 changes: 1 addition & 1 deletion codeCore/src/prog8/code/ast/AstPrinter.kt
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Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ fun printAst(root: PtNode, skipLibraries: Boolean, output: (text: String) -> Uni
val bank = if(node.address.constbank!=null) "@bank ${node.address.constbank}"
else if(node.address.varbank!=null) "@bank ${node.address.varbank?.name}"
else ""
str + "romsub $bank ${node.address.address.toHex()} = ${node.name}($params) $clobbers $returns"
str + "extsub $bank ${node.address.address.toHex()} = ${node.name}($params) $clobbers $returns"
}
}
is PtBlock -> {
Expand Down
4 changes: 2 additions & 2 deletions codeCore/src/prog8/code/optimize/Optimizer.kt
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@@ -1,6 +1,6 @@
package prog8.code.optimize

import prog8.code.StRomSub
import prog8.code.StExtSub
import prog8.code.SymbolTable
import prog8.code.ast.*
import prog8.code.core.*
Expand Down Expand Up @@ -39,7 +39,7 @@ private fun optimizeAssignTargets(program: PtProgram, st: SymbolTable, errors: I
}
if(functionName!=null) {
val stNode = st.lookup(functionName)
if (stNode is StRomSub) {
if (stNode is StExtSub) {
require(node.children.size==stNode.returns.size+1) {
"number of targets must match return values"
}
Expand Down
2 changes: 1 addition & 1 deletion codeGenCpu6502/src/prog8/codegen/cpu6502/AsmGen.kt
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Expand Up @@ -202,7 +202,7 @@ private fun PtIdentifier.prefix(parent: PtNode, st: SymbolTable): PtIdentifier {

val prefixType = when(target!!.type) {
StNodeType.BLOCK -> 'b'
StNodeType.SUBROUTINE, StNodeType.ROMSUB -> 's'
StNodeType.SUBROUTINE, StNodeType.EXTSUB -> 's'
StNodeType.LABEL -> 'l'
StNodeType.STATICVAR, StNodeType.MEMVAR -> 'v'
StNodeType.CONSTANT -> 'c'
Expand Down
14 changes: 7 additions & 7 deletions codeGenCpu6502/src/prog8/codegen/cpu6502/IfElseAsmGen.kt
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@@ -1,6 +1,6 @@
package prog8.codegen.cpu6502

import prog8.code.StRomSub
import prog8.code.StExtSub
import prog8.code.SymbolTable
import prog8.code.ast.*
import prog8.code.core.*
Expand All @@ -17,7 +17,7 @@ internal class IfElseAsmGen(private val program: PtProgram,

fun translate(stmt: PtIfElse) {
require(stmt.condition.type.isBool)
checkNotRomsubReturnsStatusReg(stmt.condition)
checkNotExtsubReturnsStatusReg(stmt.condition)

val jumpAfterIf = stmt.ifScope.children.singleOrNull() as? PtJump

Expand Down Expand Up @@ -47,7 +47,7 @@ internal class IfElseAsmGen(private val program: PtProgram,
if(stmt.hasElse())
throw AssemblyError("not prefix in ifelse should have been replaced by swapped if-else blocks")
else {
checkNotRomsubReturnsStatusReg(prefixCond.value)
checkNotExtsubReturnsStatusReg(prefixCond.value)
assignConditionValueToRegisterAndTest(prefixCond.value)
return if (jumpAfterIf != null)
translateJumpElseBodies("beq", "bne", jumpAfterIf, stmt.elseScope)
Expand Down Expand Up @@ -138,12 +138,12 @@ internal class IfElseAsmGen(private val program: PtProgram,
}
}

private fun checkNotRomsubReturnsStatusReg(condition: PtExpression) {
private fun checkNotExtsubReturnsStatusReg(condition: PtExpression) {
val fcall = condition as? PtFunctionCall
if(fcall!=null && fcall.type.isBool) {
val romsub = st.lookup(fcall.name) as? StRomSub
if(romsub!=null && romsub.returns.any { it.register.statusflag!=null }) {
throw AssemblyError("if romsub() that returns a status register boolean should have been changed into a Conditional branch such as if_cc")
val extsub = st.lookup(fcall.name) as? StExtSub
if(extsub!=null && extsub.returns.any { it.register.statusflag!=null }) {
throw AssemblyError("if extsub() returning a status register boolean should have been changed into a Conditional branch such as if_cc")
}
}
}
Expand Down
18 changes: 9 additions & 9 deletions codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AssignmentAsmGen.kt
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
package prog8.codegen.cpu6502.assignment

import prog8.code.StMemVar
import prog8.code.StRomSub
import prog8.code.StRomSubParameter
import prog8.code.StExtSub
import prog8.code.StExtSubParameter
import prog8.code.StStaticVariable
import prog8.code.ast.*
import prog8.code.core.*
Expand Down Expand Up @@ -39,7 +39,7 @@ internal class AssignmentAsmGen(
val values = assignment.value as? PtFunctionCall
?: throw AssemblyError("only function calls can return multiple values in a multi-assign")

val sub = asmgen.symbolTable.lookup(values.name) as? StRomSub
val sub = asmgen.symbolTable.lookup(values.name) as? StExtSub
?: throw AssemblyError("only asmsubs can return multiple values")

require(sub.returns.size>=2)
Expand All @@ -64,11 +64,11 @@ internal class AssignmentAsmGen(
}

private fun assignStatusFlagsAndRegistersResults(
statusFlagResults: List<Pair<StRomSubParameter, PtNode>>,
registersResults: List<Pair<StRomSubParameter, PtNode>>
statusFlagResults: List<Pair<StExtSubParameter, PtNode>>,
registersResults: List<Pair<StExtSubParameter, PtNode>>
) {

fun needsToSaveA(registersResults: List<Pair<StRomSubParameter, PtNode>>): Boolean =
fun needsToSaveA(registersResults: List<Pair<StExtSubParameter, PtNode>>): Boolean =
if(registersResults.isEmpty())
false
else if(registersResults.all { (it.second as PtAssignTarget).identifier!=null})
Expand All @@ -91,12 +91,12 @@ internal class AssignmentAsmGen(
}
}

private fun assignOnlyTheStatusFlagsResults(saveA: Boolean, statusFlagResults: List<Pair<StRomSubParameter, PtNode>>) {
private fun assignOnlyTheStatusFlagsResults(saveA: Boolean, statusFlagResults: List<Pair<StExtSubParameter, PtNode>>) {
// assigning flags to their variables targets requires load-instructions that destroy flags
// so if there's more than 1, we need to save and restore the flags
val saveFlags = statusFlagResults.size>1

fun hasFlag(statusFlagResults: List<Pair<StRomSubParameter, PtNode>>, flag: Statusflag): PtAssignTarget? {
fun hasFlag(statusFlagResults: List<Pair<StExtSubParameter, PtNode>>, flag: Statusflag): PtAssignTarget? {
for ((returns, target) in statusFlagResults) {
if(returns.register.statusflag!! == flag)
return target as PtAssignTarget
Expand All @@ -121,7 +121,7 @@ internal class AssignmentAsmGen(
if(saveA) asmgen.out(" pla")
}

private fun assignRegisterResults(registersResults: List<Pair<StRomSubParameter, PtNode>>) {
private fun assignRegisterResults(registersResults: List<Pair<StExtSubParameter, PtNode>>) {
registersResults.forEach { (returns, target) ->
target as PtAssignTarget
if(!target.void) {
Expand Down
8 changes: 4 additions & 4 deletions codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
package prog8.codegen.intermediate

import prog8.code.StRomSub
import prog8.code.StRomSubParameter
import prog8.code.StExtSub
import prog8.code.StExtSubParameter
import prog8.code.ast.*
import prog8.code.core.*
import prog8.intermediate.*
Expand All @@ -14,7 +14,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
val values = assignment.value as? PtFunctionCall
?: throw AssemblyError("only function calls can return multiple values in a multi-assign")

val sub = codeGen.symbolTable.lookup(values.name) as? StRomSub
val sub = codeGen.symbolTable.lookup(values.name) as? StExtSub
?: throw AssemblyError("only asmsubs can return multiple values")

val result = mutableListOf<IRCodeChunkBase>()
Expand Down Expand Up @@ -46,7 +46,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
}
}

private fun assignCpuRegister(returns: StRomSubParameter, regNum: Int, target: PtAssignTarget): IRCodeChunks {
private fun assignCpuRegister(returns: StExtSubParameter, regNum: Int, target: PtAssignTarget): IRCodeChunks {
val result = mutableListOf<IRCodeChunkBase>()
val loadCpuRegInstr = when(returns.register.registerOrPair) {
RegisterOrPair.A -> IRInstruction(Opcode.LOADHA, IRDataType.BYTE, reg1=regNum)
Expand Down
12 changes: 6 additions & 6 deletions codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
package prog8.codegen.intermediate

import prog8.code.StNode
import prog8.code.StRomSub
import prog8.code.StExtSub
import prog8.code.StSub
import prog8.code.ast.*
import prog8.code.core.*
Expand Down Expand Up @@ -589,7 +589,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
else
ExpressionCodeResult(result, returnRegSpec!!.dt, returnRegSpec.registerNum, -1)
}
is StRomSub -> {
is StExtSub -> {
val result = mutableListOf<IRCodeChunkBase>()
addInstr(result, IRInstruction(Opcode.PREPARECALL, immediate = callTarget.parameters.size), null)
// assign the arguments
Expand Down Expand Up @@ -622,7 +622,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
}

if(callTarget.returns.size>1)
return callRomSubWithMultipleReturnValues(callTarget, fcall, argRegisters, result)
return callExtSubWithMultipleReturnValues(callTarget, fcall, argRegisters, result)

// return a single value (or nothing)
val returnRegSpec = if(fcall.void) null else {
Expand Down Expand Up @@ -751,8 +751,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
}
}

private fun callRomSubWithMultipleReturnValues(
callTarget: StRomSub,
private fun callExtSubWithMultipleReturnValues(
callTarget: StExtSub,
fcall: PtFunctionCall,
argRegisters: MutableList<FunctionCallArgs.ArgumentSpec>,
result: MutableList<IRCodeChunkBase>
Expand All @@ -775,7 +775,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
fcallArgs = FunctionCallArgs(argRegisters, returnRegisters)
)
}
else TODO("romsub with banked address got called ${callTarget.name}")
else TODO("extsub with banked address got called ${callTarget.name}")
}
addInstr(result, call, null)
val resultRegs = returnRegisters.filter{it.dt!=IRDataType.FLOAT}.map{it.registerNum}
Expand Down
4 changes: 2 additions & 2 deletions codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt
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Expand Up @@ -1702,9 +1702,9 @@ class IRCodeGen(
}
is PtAsmSub -> {
if(child.address!=null) {
// romsub. No codegen needed: calls to this are jumping straight to the address.
// extmsub. No codegen needed: calls to this are jumping straight to the address.
require(child.children.isEmpty()) {
"romsub should be empty at ${child.position}"
"extsub should be empty at ${child.position}"
}
} else {
// regular asmsub
Expand Down
8 changes: 4 additions & 4 deletions codeGenIntermediate/test/TestVmCodeGen.kt
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Original file line number Diff line number Diff line change
Expand Up @@ -527,9 +527,9 @@ class TestVmCodeGen: FunSpec({
irChunks.size shouldBe 1
}

test("romsub allowed in ir-codegen") {
test("extsub allowed in ir-codegen") {
//main {
// romsub $5000 = routine()
// extsub $5000 = routine()
//
// sub start() {
// routine()
Expand All @@ -538,8 +538,8 @@ class TestVmCodeGen: FunSpec({
val codegen = VmCodeGen()
val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
val romsub = PtAsmSub("routine", PtAsmSub.Address(null, null, 0x5000u), setOf(CpuRegister.Y), emptyList(), emptyList(), false, Position.DUMMY)
block.add(romsub)
val extsub = PtAsmSub("routine", PtAsmSub.Address(null, null, 0x5000u), setOf(CpuRegister.Y), emptyList(), emptyList(), false, Position.DUMMY)
block.add(extsub)
val sub = PtSub("start", emptyList(), null, Position.DUMMY)
val call = PtFunctionCall("main.routine", true, DataType.forDt(BaseDataType.UNDEFINED), Position.DUMMY)
sub.add(call)
Expand Down
6 changes: 3 additions & 3 deletions compiler/res/prog8lib/atari/syslib.p8
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Original file line number Diff line number Diff line change
Expand Up @@ -12,9 +12,9 @@ atari {
&uword COLCRS = 85
&ubyte ROWCRS = 84

romsub $F24A = getchar() -> ubyte @A
romsub $F2B0 = outchar(ubyte character @ A)
romsub $F2FD = waitkey() -> ubyte @A
extsub $F24A = getchar() -> ubyte @A
extsub $F2B0 = outchar(ubyte character @ A)
extsub $F2FD = waitkey() -> ubyte @A

}

Expand Down
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