Skip to content

Commit

Permalink
Updated docs - Alternative simulators + misc
Browse files Browse the repository at this point in the history
  • Loading branch information
jchabloz committed Mar 8, 2024
1 parent d5a9967 commit f5c8015
Show file tree
Hide file tree
Showing 2 changed files with 32 additions and 12 deletions.
32 changes: 24 additions & 8 deletions docs/src/intro.rst
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ to trying and compile Verisocks:
packaged version provided with your favorite distro.
* GCC C or C++ compiler

.. note::
.. note::

Older GCC versions will most likely complain about the variadic macros used
for logging purposes. These warnings can normally be safely ignored...
Expand Down Expand Up @@ -68,6 +68,11 @@ not to impact your system's Python packages.
pip install <path to your verisocks folder>/python
.. note::

The main advantage of Verisock's socket interface is its versatility. The
Python client provided with the code can serve as a reference implementation
that can easily be replicated in any language with an API for TCP sockets.

Run the examples
----------------
Expand Down Expand Up @@ -138,12 +143,23 @@ have to typically be:
variable rising edge),
* etc...

.. note::
.. _sec_alternative_simulators:

Alternative simulators
**********************

Note that while the Verisocks PLI application has been developed targeting
specifically Icarus as a verilog simulator, there is no known reason that
it would not be working as well with any other simulator that is supporting
the VPI interface standard, including mainstream commercial simulators. I
will gladly accept any contribution that may confirm or infirm this
statement...
While the Verisocks PLI application has been developed targeting specifically
Icarus as a verilog simulator, there is no known reason that it would not be
working as well with any other simulator that is supporting the VPI normative
interface (as defined in `IEEE Std 1364
<https://ieeexplore.ieee.org/document/1620780>`_ and `IEEE Std 1800
<https://ieeexplore.ieee.org/document/10458102>`_), including mainstream
commercial simulators.

.. note::
I will gladly accept any contribution to test Verisocks with other
simulators.
As of now, I have only successfully tested it with Cadence's XCelium 64
29.03. As soon as I get more material, I will make a short tutorial for it.
My next target will be Tachyon's CVC. If anybody is able to test it with
QuestaSim...
12 changes: 8 additions & 4 deletions docs/src/release_notes.rst
Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,15 @@ version numbering system follows the `semantic versioning
1.1.1 - Ongoing
***************

* Modified :py:meth:`Verisocks.connect()
<verisocks.verisocks.Verisocks.connect>` method to include multiple, delayed
connection trials. Examples and test have been simplified accordingly.
* Modified :py:class:`Verisocks<verisocks.verisocks.Verisocks>` constructor and
:py:meth:`Verisocks.connect() <verisocks.verisocks.Verisocks.connect>` method
to include arguments for multiple, delayed connection trials. Examples and
test have been simplified accordingly.
* Added correct management of system call interrupts while waiting on client
connection in the server code.
connection in the server code (see
https://www.gnu.org/software/libc/manual/html_node/Interrupted-Primitives.html
for details).
* Added section :ref:`sec_alternative_simulators`.

1.1.0 - 2024-02-07
******************
Expand Down

0 comments on commit f5c8015

Please sign in to comment.