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1. rv32i-1cycle-cpu rv32i-1cycle-cpu Public

   A single-cycle implementation of the 32-bit RISC-V RV32I instruction set (Integer Extension) in SystemVerilog for learning datapath and control signal flow.

   SystemVerilog

2. rv32im-5stage-cpu rv32im-5stage-cpu Public

   A 5-stage, in order, pipelined upgrade of the single-cycle RV32I CPU in SystemVerilog. Includes the RISC-V "M" extension (multiply/divide) with multi-cycle arithmetic units, a full hazard unit with…

   SystemVerilog