GitHub - jinfeng-zhuang/mpeg2fpga: An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.

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An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.

www.kdvelectronics.eu/mpeg2fpga/mpeg2fpga.html

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
bench		bench
doc		doc
rtl		rtl
tools		tools
2do.txt		2do.txt
Makefile		Makefile
README		README

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This is a mpeg2 video core. To run a testbench:

1. Download a sample video

cd tools/streams
wget ftp://ftp.tek.com/tv/test/streams/Element/MPEG-Video/625/susi_015.m2v
mv susi_015.m2v stream-susi.mpg

2. Install Icarus verilog

apt-get install iverilog

3. Run testbench

cd bench/iverilog
Verify top of Makefile looks like this:

STREAM = ../../tools/streams/stream-susi.mpg
MODELINE = MODELINE_SIF

make clean test

Directory ought to fill with .ppm files.