Merge branch 'next-time'

jlpteaching · Dec 21, 2017 · 4892af6 · 4892af6
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diff --git a/hw1/hw1.rst b/hw1/hw1.rst
@@ -8,6 +8,8 @@ ECS 201A - Homework 1
 Due: Monday, 9 October 2017 at 3:10 PM
 --------------------------------------
 
+**FOR NEXT TIME** Add details about how I'm going to grade assignments.
+
 Submission of your code and your report will be done through Canvas_.
 See the Submission_ section below for more information.
 

diff --git a/hw2/hw2.rst b/hw2/hw2.rst
@@ -5,6 +5,9 @@
 ECS 201A - Homework 2
 =====================
 
+For next time: Make them implement a small victim cache on the direct-mapped version to show how much victim caches help.
+Also, looking at 2-way and 4-way would be better than not.
+
 Due: Monday, 23 October 2017 at 3:10 PM
 ---------------------------------------
 

diff --git a/hw3/hw3.rst b/hw3/hw3.rst
@@ -136,6 +136,8 @@ Answer the following question in your report.
 
 2. Does loop unrolling provide an improvement? Answer for each function. What kind of hazard does loop unrolling decrease?
 
+3. How many times should you unroll the loops? Is it the same for each loop? What happens if you don't unroll enough or unroll too much?
+
 .. _Wikipedia: https://en.wikipedia.org/wiki/Loop_unrolling
 .. _good YouTube videos: https://www.youtube.com/watch?v=hsQj7n-8Q3A
 

diff --git a/hw5/hw5.rst b/hw5/hw5.rst
@@ -1,6 +1,9 @@
 :Author: Jason Lowe-Power
 :Editor: Justin Perona
 
+(TO DO) Convert the Reversi code from C to C++.
+Also, potentially find a machine with 16+ cores to compare on, sort of like what David Wood did with the Xeon Phi?
+
 =====================
 ECS 201A - Homework 5
 =====================

diff --git a/syllabus/syllabus.rst b/syllabus/syllabus.rst
@@ -112,7 +112,8 @@ You will need to have third-party cookies enabled to access the videos.
 Prerequisites
 -------------
 
-Undergraduate computer architecture course (e.g., ECS 154B).
+Undergraduate computer architecture course (e.g., ECS 154B)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 I am going to assume you have knowledge of ISAs, simple pipelining, simple caching, and high-level computer organization.
 These basics are covered in D. A. Patterson and J. L. Hennessy, `Computer Organization and Design: The Hardware/Software Interface`_.
@@ -121,8 +122,25 @@ Some of these topics are covered in the appendices of our Hennessy and Patterson
 For instance, Appendix A gives a great overview of ISA design and implications.
 If you find you do not have enough background on a topic, start by checking the appendices of the book.
 
+If you do not have this background, succeeding in this class will be hard.
+It is possible to catch up by reading along with the Patterson and Hennessy book and the appendecies.
+However, you should expect to put in the amount of time for two classes to catch up.
+
 .. _`Computer Organization and Design: The Hardware/Software Interface`: http://dl.acm.org/citation.cfm?id=2568134
 
+Programming experience
+~~~~~~~~~~~~~~~~~~~~~~
+
+We will be using simulation for many of the assignments in this course. 
+Simulators are large software projects.
+This course will be extra work if you do not have a strong coding background.
+
+Specifically, we will be using gem5_ which is written in C++ and Python.
+You should have experience programming in C or C++ and Python to succeed in this course.
+If you do not have this experience, expect to spend significant time on the assignments since you will be learning both computer architecture and a programming language.
+
+.. _gem5: http://gem5.googlesource.com/
+
 Class Format
 ------------