hw: Minor fix in hw2 docstring

jlpteaching · Dec 30, 2024 · ddd9cb1 · ddd9cb1
1 parent 690a8fc
commit ddd9cb1
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/assignment-2/components/__init__.py b/assignment-2/components/__init__.py
@@ -31,10 +31,10 @@ def __init__(self):
 
 class DDR4(ChanneledMemory):
     """
-    HW1DDR4_2400_8x8 models a 1 GiB single channel DDR4 DRAM memory with a data
+    DDR4 models a 1 GiB single channel DDR4 DRAM memory with a data
     bus clocked at 2400MHz.
 
-    The theoretical peak bandwidth of DDR3 is 19.2 GB/s.
+    The theoretical peak bandwidth of DDR4 is 19.2 GB/s.
     """
     def __init__(self):
         super().__init__(DDR4_2400_8x8, 1, 128, size="1GiB")