Final Project: Full-Duplex RGB Image Data Exchange over UART

Course: Design Verification (Chip Design)
Student: Asaf Kamber
Institution: Reichman University

Project Overview

This project implements a complete system for receiving and transmitting RGB images of selectable dimensions between an FPGA (Nexys A7-100T) and a PC over UART, with back-pressure controlled data-pipe. Image TX (single pixel per message) is implemented end-to-end and verified in simulation and on hardware.

Directory Structure

design-rtl-final-project/
├── sv-code/              # SystemVerilog source
│   ├── src/              # RTL (fpga_top, uart/, memory/, control/, debug/, utils/)
│   ├── sim/              # Testbench (tb_fpga_top.sv)
│   └── pkg/              # Packages (sys_pkg, img_pkg, fifo_pkg)
├── xdc/                  # Nexys A7-100T constraints
├── mem-files/            # ROM init (.mem) for R, G, B
├── scripts/              # Vivado TCL, Python (UART/capture), see scripts/README.md
├── docs/
│   ├── reference/        # Block diagram, data flow, FSM .md; VIVADO_GUIDE, WAVEFORM_GUIDE, etc.
│   ├── diagrams/         # register_map.csv, message_protocol.csv, resource_utilization.csv
│   └── reports/          # utilization.txt, utilization_hier.txt, timing.txt, power.txt
├── figures/              # Report figures (block diagram, FSM, waveform)
├── FINAL_REPORT.md       # Lab 10 final report
└── README.md             # This file

Note: The Vivado project is not in the repo. Regenerate it with scripts/create_vivado_project.tcl (see Build Instructions below).

Status Summary

Priority	Feature	Status
P1 (MUST)	Image TX: single pixel per message, format {R<row>, C<col>, P<R,G,B>}	✅ Implemented and hardware-verified
P2	Register read (SYS, IMG, FIFO RGF)	✅ Implemented and verified
P3	Register write	✅ Implemented and verified
P4	Image RX (burst write)	⚠️ Parser only
Bonus	Image burst TX, >5 MHz baud	⏸️ Not implemented

• Simulation: Testbench tb_fpga_top.sv (3 UART tests); DUT fpga_top #(.SIM(1)); all pass.
• Synthesis & implementation: Vivado 2020.2; part xc7a100tcsg324-1. Timing met (WNS 2.184 ns), utilization ~2% LUTs / 0.64% FFs / 8.89% BRAM.
• Hardware: Verified on Nexys A7-100T with Python scripts (register R/W, image TX, capture).

Build Instructions

1. Regenerate Vivado project

From the repo root (no Vivado project is committed):

vivado -mode batch -source scripts/create_vivado_project.tcl

This creates the project and adds sources, constraints, and mem files. Open the generated .xpr in Vivado.

2. Simulation

In Vivado: add sv-code/sim/tb_fpga_top.sv as simulation source, set top to tb_fpga_top, run behavioral simulation. Optional waveform setup: source scripts/setup_waveform_detailed.tcl after opening the simulation.

3. Synthesis and bitstream

In Vivado: Run Synthesis → Run Implementation → Generate Bitstream. Constraints and part are set by create_vivado_project.tcl.

Key Technical Details

• UART: 57600 baud, 8E1 (even parity). MAC/PHY split; RTS/CTS in RTL.
• Clock: Single 100 MHz system clock (no PLL; baud >5 MHz not implemented).
• Image path: ROM (3×16K×8) → async FIFO (1024×24) → TX sequencer → message composer → UART TX.
• Address map: SYS_RGF 0x03_XXXX, IMG_RGF 0x04_XXXX, FIFO_RGF 0x05_XXXX. See docs/diagrams/register_map.csv.

Message Protocol (summary)

• PC→FPGA: Register write {W<A2,A1,A0>, V<Ø,DH,DL>}, Register read {R<A2,A1,A0>}, Single pixel write {W<addr>, P<R,G,B>}, Burst write (parser only).
• FPGA→PC: Single pixel read {R<row>, C<col>, P<R,G,B>} (image TX). See docs/diagrams/message_protocol.csv.

Deliverables

• RTL and testbench (SystemVerilog)
• Simulation verified (tb_fpga_top, 3 tests pass)
• Synthesis and implementation (timing, utilization, power reports in docs/reports/)
• Block diagram, data flow, FSM diagrams (docs/reference/01–03*.md, docs/diagrams/)
• Register map and message protocol (docs/diagrams/*.csv)
• Hardware testing (UART, registers, image TX, capture script)
• Final report (FINAL_REPORT.md)

Documentation

Document	Description
FINAL_REPORT.md	Lab 10 final report (requirements, data flow, timing/util/power, challenges)
docs/reference/VIVADO_GUIDE.md	Vivado workflow, synthesis, timing, simulation
docs/reference/FILE_LIST.md	Compilation order and file list
docs/reference/NEXT_STEPS.md	Report checklist and fixes list
docs/reference/HARDWARE_DEBUG.md	Hardware bring-up, UART settings, LEDs
docs/reference/WAVEFORM_GUIDE.md	Simulation waveform interpretation
docs/reference/	Block diagram, data flow, FSM (01–03 *.md)
docs/diagrams/	register_map.csv, message_protocol.csv, resource_utilization.csv
docs/reports/	utilization.txt, utilization_hier.txt, timing.txt, power.txt
scripts/README.md	Scripts overview (Vivado TCL, Python)

References

• Lab 10 instructions (full-duplex RGB image over UART)
• Labs 7–9: UART MAC/PHY, image pipeline, async FIFO
• Nexys A7-100T Reference Manual
• Vivado 2020.2 documentation

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Last updated: 2026-02 — Synthesis and implementation complete; hardware verified.