arm: bsp: add NXP S32K5 platform support #18
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
jkloetzke
reviewed
Dec 19, 2025
Contributor
jkloetzke
left a comment
jkloetzke
left a comment
There was a problem hiding this comment.
Thanks! LGTM in general. Only the RAM_BASE handling might need some attention...
src/kern/arm/bsp/s32k5/Kconfig
Outdated
Comment on lines
9
to
18
| config PF_S32K5_AUTO_RAM_BASE | ||
| bool "Automatically choose RAM_BASE" | ||
| default y | ||
| help | ||
| Use default RAM base address, CPE SRAM0. | ||
|
|
||
| config PF_S32K5_MANUAL_RAM_BASE | ||
| hex "Custom RAM_BASE" | ||
| depends on !PF_S32K5_AUTO_RAM_BASE | ||
| default 0x22000000 |
Contributor
There was a problem hiding this comment.
As there is only a single cluster, we could simplify this IMHO:
Suggested change
| config PF_S32K5_AUTO_RAM_BASE | |
| bool "Automatically choose RAM_BASE" | |
| default y | |
| help | |
| Use default RAM base address, CPE SRAM0. | |
| config PF_S32K5_MANUAL_RAM_BASE | |
| hex "Custom RAM_BASE" | |
| depends on !PF_S32K5_AUTO_RAM_BASE | |
| default 0x22000000 | |
| config PF_S32K5_RAM_BASE | |
| hex "Kernel load address" | |
| default 0x22000000 | |
| help | |
| Start address of the kernel image. Defaults to start of CPE SRAM0. |
Contributor
Author
There was a problem hiding this comment.
agreed, no need for two options on this platform
src/kern/arm/bsp/s32k5/Modules
Outdated
| PREPROCESS_PARTS += generic_tickless_idle arm_generic_timer pic_gic | ||
| INTERFACES_KERNEL += generic_timer irq_mgr_multi_chip | ||
|
|
||
| RAM_PHYS_BASE := $(strip $(CONFIG_PF_S32K5_MANUAL_RAM_BASE)) |
Contributor
There was a problem hiding this comment.
I'm not sure this works if PF_S32K5_AUTO_RAM_BASE is set. Anyway, if we remove PF_S32K5_AUTO_RAM_BASE then we could do the following:
Suggested change
| RAM_PHYS_BASE := $(strip $(CONFIG_PF_S32K5_MANUAL_RAM_BASE)) | |
| RAM_PHYS_BASE := $(CONFIG_PF_S32K5_RAM_BASE) |
Add platform support for NXP S32K5 running on the CPE subsystem. This includes BSP definitions and initialization hooks required for L4Re Microhypervisor bring-up on CPE. The CPE subsystem features a single Cortex-R52 cluster with two cores operating in split-lock mode. Single core and AMP is supported. Unlike other NXP S32 platforms, CPE MRU instances route interrupts as GIC SPIs, so MRU virtualization is not required. Change-Id: Ibfe223e6be7deb36ba86010c7ce9162ff04cd3dd Co-Authored-By: Flavius Vlasa <flavius.vlasa@nxp.com> Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
manuargue
force-pushed
the
upstream-s32k5
branch
from
86fde59 to
6eee388
Compare
jkloetzke
approved these changes
Dec 19, 2025
Contributor
jkloetzke
left a comment
jkloetzke
left a comment
There was a problem hiding this comment.
Thanks. I'll queue the PR for merging internally...
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Add platform support for NXP S32K5 running on the CPE subsystem. This includes BSP definitions and initialization hooks required for L4Re Microhypervisor bring-up on CPE.
The CPE subsystem features a single Cortex-R52 cluster with two cores operating in split-lock mode. Single core and AMP is supported. Unlike other NXP S32 platforms, CPE MRU instances route interrupts as GIC SPIs, so MRU virtualization is not required.