Add support for 'fence.i' instruction #2622
xThaidmain.yml
on: pull_request
Synthesize full core
40s
Build regression tests (riscv-tests)
42s
Build regression tests (riscv-arch-test)
47s
Run unit tests
8m 28s
Check code formatting and typing
35s
Run regression tests (riscv-tests)
3m 30s
Run regression tests (riscv-arch-test)
12m 22s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
Expired
|
392 KB |
|