Superscalar frontend #630
Superscalar frontend #630
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This reverts commit dc1fd19.
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This FENCE test fail is weird. Is this a LSU bug, which somehow wasn't detected by all the other tests? |
| self.resume = Method(i=self.gen_params.get(FetchLayouts).resume) | ||
| self.stall_exception = Method() | ||
| self.stall_exception.add_conflict(self.resume, Priority.LEFT) | ||
| It is a temporary workaround for a fetch buffer until the rest of the core becomes |
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Maybe it is a workaround, but general. It should be in transactron library in my opinion.
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If we have another use case, I'll be happy to move it.
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| # For now assume that the fetch block is 4 bytes long (a machine word). | ||
| assert self.gen_params.fetch_block_bytes == 4 | ||
| self.clean.add_conflict(self.write, Priority.LEFT) |
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Clean is last definition in module, so it is not needed to add conflicts.
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add_conflict also prohibits the methods from running simultaneously. I am using this semantics in the fetch unit to guarantee that whenever we have a stall signal, no instruction can leave the fetch unit (even in the same cycle).
| ("fibonacci", "fibonacci.asm", 1200 * 2, {2: 2971215073}, basic_core_config), | ||
| ("fibonacci_mem", "fibonacci_mem.asm", 610 * 2, {3: 55}, basic_core_config), | ||
| ("fibonacci", "fibonacci.asm", 500, {2: 2971215073}, basic_core_config), | ||
| ("fibonacci_mem", "fibonacci_mem.asm", 400, {3: 55}, basic_core_config), | ||
| ("csr", "csr.asm", 200, {1: 1, 2: 4}, full_core_config), | ||
| ("exception", "exception.asm", 200 * 2, {1: 1, 2: 2}, basic_core_config), | ||
| ("exception_mem", "exception_mem.asm", 200 * 2, {1: 1, 2: 2}, basic_core_config), |
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Is there possibility to reduce rest of test duration?
Benchmarks: https://github.com/xThaid/coreblocks/actions/runs/8599901154
TODO:
riscvmodeldependency - code ininstr.pyfor encoding instructions doesn't work yet (Refactor RISC-V instruction models #631)Pipedata structure somewhere else. (Add Pipe module #639)ArrayLayouts(Support ArrayLayouts in assign #640)