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Support for STM32 #302
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Support for STM32 #302
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A timer prescaler is typically loaded without a guard, meaning that it won't take event until the next update event of the clock. This is meant to ensure the prescaler doesn't take effect mid-phase, which could cause strange artifacts in your application. When you enable the peripheral, it will start with whatever was in the prescaler register at the time it was enabled, possibly leading to a large delay before the timer ISR fires. The new prescaler value will be loaded after the preceding update event.
I'm not intimately familiar with this chipset, but generally hardware peripherals are configured first and then enabled. You may consider loading the prescaler before you enable the counter. If that doesn't work, a reset is fine, but I suggest a simpler comment "reset to effect new prescaler".
This is important in safety-critical systems, you need to know when your I/O is stable and safe to use. This is known as "I/O stability".
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LGTM! But consider changing the prescaler handling.
The function initializes the clock and sets up the timer. Consider changing the prescaler handling as suggested in the existing comment.
Committable suggestion
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This method sleeps; what happens if an async event happens during the sleep, and before it is reset here? Is the event lost?
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Does this disable all interrupts? If so, does this affect timer/counters?
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What units is this #def? Should it be a const instead?
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I kinda just copied this over when I compared it against the rp2040 platform - I wasnt sure what this was used for so I kept it just incase. If its not used in LF proper, ill just delete it