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[circt-bmc][VerifToSMT] Pop existing assertions on each cycle (#7900)
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lib/Conversion/VerifToSMT/VerifToSMT.cpp

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@@ -258,6 +258,9 @@ struct VerifBoundedModelCheckingOpConversion
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ValueRange initVals =
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rewriter.create<func::CallOp>(loc, initFuncOp)->getResults();
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// Initial push
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rewriter.create<smt::PushOp>(loc, 1);
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// InputDecls order should be <circuit arguments> <state arguments>
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// <wasViolated>
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// Get list of clock indexes in circuit args
@@ -297,6 +300,10 @@ struct VerifBoundedModelCheckingOpConversion
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auto forOp = rewriter.create<scf::ForOp>(
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loc, lowerBound, upperBound, step, inputDecls,
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[&](OpBuilder &builder, Location loc, Value i, ValueRange iterArgs) {
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// Drop existing assertions
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builder.create<smt::PopOp>(loc, 1);
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builder.create<smt::PushOp>(loc, 1);
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// Execute the circuit
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ValueRange circuitCallOuts =
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builder

test/Conversion/VerifToSMT/verif-to-smt.mlir

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@@ -90,6 +90,7 @@ func.func @test_lec(%arg0: !smt.bv<1>) -> (i1, i1, i1) {
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// CHECK-LABEL: func.func @test_bmc() -> i1 {
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// CHECK: [[BMC:%.+]] = smt.solver
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// CHECK: [[INIT:%.+]]:2 = func.call @bmc_init()
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// CHECK: smt.push 1
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// CHECK: [[F0:%.+]] = smt.declare_fun : !smt.bv<32>
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// CHECK: [[F1:%.+]] = smt.declare_fun : !smt.bv<32>
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// CHECK: [[C0_I32:%.+]] = arith.constant 0 : i32
@@ -98,6 +99,8 @@ func.func @test_lec(%arg0: !smt.bv<1>) -> (i1, i1, i1) {
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// CHECK: [[FALSE:%.+]] = arith.constant false
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// CHECK: [[TRUE:%.+]] = arith.constant true
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// CHECK: [[FOR:%.+]]:5 = scf.for [[ARG0:%.+]] = [[C0_I32]] to [[C10_I32]] step [[C1_I32]] iter_args([[ARG1:%.+]] = [[INIT]]#0, [[ARG2:%.+]] = [[F0]], [[ARG3:%.+]] = [[F1]], [[ARG4:%.+]] = [[INIT]]#1, [[ARG5:%.+]] = [[FALSE]])
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// CHECK: smt.pop 1
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// CHECK: smt.push 1
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// CHECK: [[CIRCUIT:%.+]]:2 = func.call @bmc_circuit([[ARG1]], [[ARG2]], [[ARG3]])
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// CHECK: [[SMTCHECK:%.+]] = smt.check sat {
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// CHECK: smt.yield [[TRUE]]

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