[FIRRTL] Clock gate extraction work w/ prefixing (#7946)

Weaken the check used by the `ExtractInstances` pass to determine what is
a clock gate.  Change this from requiring that the defname of an external
module is exactly "EICG_wrapper" to instead only needing to end with
"EICG_wrapper".  This is done so that this will work with Chisel-time
prefixing and that we would actually _like_ to prefix these clock gates.

Commentary: this string matching is terrible.  I realize that.  However,
this is a legacy API that is intending to be replaced.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Author: seldridge

docs/Dialects/FIRRTL/FIRRTLAnnotations.md

@@ -862,9 +862,9 @@ Example:
 | group       | string | Name of an optional wrapper module under which to group extracted instances |
 
 This annotation causes the `ExtractInstances` pass to move instances of
-extmodules with defname `EICG_wrapper` upwards in the hierarchy, either out of
-the DUT if `group` is omitted or empty, or into a submodule of the DUT with the
-name given in `group`. The wiring prefix is hard-coded to `clock_gate`.
+extmodules whose defnames end in `EICG_wrapper` upwards in the hierarchy, either
+out of the DUT if `group` is omitted or empty, or into a submodule of the DUT
+with the name given in `group`. The wiring prefix is hard-coded to `clock_gate`.
 
 Applies to the circuit.
 

lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp

@@ -352,14 +352,15 @@ void ExtractInstancesPass::collectAnnos() {
     collectAnno(inst, instAnnos[0]);
   });
 
-  // If clock gate extraction is requested, find instances of extmodules with
-  // the corresponding `defname` and mark them as to be extracted.
-  // TODO: This defname really shouldn't be hardcoded here. Make this at least
-  // somewhat configurable.
+  // If clock gate extraction is requested, find instances of extmodules which
+  // have a defname that ends with "EICG_wrapper".  This also allows this to
+  // compose with Chisel-time module prefixing.
+  //
+  // TODO: This defname matching is a terrible hack and should be replaced with
+  // something better.
   if (!clkgateFileName.empty()) {
-    auto clkgateDefNameAttr = StringAttr::get(&getContext(), "EICG_wrapper");
     for (auto module : circuit.getOps<FExtModuleOp>()) {
-      if (module.getDefnameAttr() != clkgateDefNameAttr)
+      if (!module.getDefnameAttr().getValue().ends_with("EICG_wrapper"))
         continue;
       LLVM_DEBUG(llvm::dbgs()
                  << "Clock gate `" << module.getModuleName() << "`\n");

test/Dialect/FIRRTL/extract-instances.mlir

@@ -751,3 +751,46 @@ firrtl.circuit "Plop_Foo" attributes {annotations = [{class = "sifive.enterprise
     firrtl.instance core sym @core @Plop_Bar()
   }
 }
+
+// Test that clock gate extraction composes with Chisel-time module prefixing.
+// Chisel may add any number of prefixes to the clock gates.  Ensure that this
+// will not block extraction.  Additionally, test that suffixes will block
+// extraction.
+//
+// CHECK-LABEL: firrtl.circuit "PrefixedClockGate"
+firrtl.circuit "PrefixedClockGate" attributes {
+  annotations = [
+    {
+      class = "sifive.enterprise.firrtl.ExtractClockGatesFileAnnotation",
+      filename = "ckgates.txt",
+      group = "ClockGates"
+    }
+  ]
+} {
+  firrtl.extmodule private @Prefix_EICG_wrapper() attributes {
+    defname = "Prefix_EICG_wrapper"
+  }
+  firrtl.extmodule private @Prefix_EICG_wrapper_Suffix() attributes {
+    defname = "Prefix_EICG_wrapper_Suffix"
+  }
+  // CHECK:      firrtl.module private @ClockGates() {
+  // CHECK-NEXT:   firrtl.instance clockGate_0 @Prefix_EICG_wrapper()
+  // CHECK-NOT:    firrtl.instance clockGate_1 @Prefix_EICG_wrapper_Suffix()
+  //
+  // CHECK:      firrtl.module @Foo
+  // CHECK-NEXT:   firrtl.instance ClockGates {{.*}} @ClockGates()
+  // CHECK-NEXT:   firrtl.instance clockGate_1 @Prefix_EICG_wrapper_Suffix()
+  firrtl.module @Foo() attributes {
+    annotations = [
+      {
+        class = "sifive.enterprise.firrtl.MarkDUTAnnotation"
+      }
+    ]
+  } {
+    firrtl.instance clockGate_0 @Prefix_EICG_wrapper()
+    firrtl.instance clockGate_1 @Prefix_EICG_wrapper_Suffix()
+  }
+  firrtl.module @PrefixedClockGate() {
+    firrtl.instance foo @Foo()
+  }
+}