[FIRRTL] Drop auxiliary MemOp builders

Remove auxiliary MemOp builders.  These had exactly one user,
`LowerTypes`, and this user switched to the tablegen-generated builders in
a previous commit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Author: seldridge

include/circt/Dialect/FIRRTL/FIRRTLDeclarations.td

@@ -258,24 +258,6 @@ def MemOp : HardwareDeclOp<"mem", [DeclareOpInterfaceMethods<CombDataflow>]> {
     $ruw `` custom<MemOp>(attr-dict) `:` qualified(type($results))
   }];
 
-  let builders = [
-    OpBuilder<(ins "::mlir::TypeRange":$resultTypes,
-                   "uint32_t":$readLatency, "uint32_t":$writeLatency,
-                   "uint64_t":$depth, "RUWAttr":$ruw,
-                   "ArrayRef<Attribute>":$portNames,
-                   CArg<"StringRef", "{}">:$name,
-                   CArg<"NameKindEnum", "NameKindEnum::DroppableName">:$nameKind,
-                   CArg<"ArrayRef<Attribute>", "{}">:$annotations,
-                   CArg<"ArrayRef<Attribute>", "{}">:$portAnnotations,
-                   CArg<"StringAttr", "StringAttr()">:$innerSym)>,
-    OpBuilder<(ins "::mlir::TypeRange":$resultTypes, "uint32_t":$readLatency,
-                   "uint32_t":$writeLatency, "uint64_t":$depth, "RUWAttr":$ruw,
-                   "ArrayRef<Attribute>":$portNames, "StringRef":$name,
-                   "NameKindEnum":$nameKind, "ArrayRef<Attribute>":$annotations,
-                   "ArrayRef<Attribute>":$portAnnotations,
-                   "hw::InnerSymAttr":$innerSym)>
-  ];
-
   let hasVerifier = 1;
 
   let hasCanonicalizer = true;

lib/Dialect/FIRRTL/FIRRTLOps.cpp

@@ -2854,50 +2854,6 @@ InstanceChoiceOp::erasePorts(OpBuilder &builder,
 // MemOp
 //===----------------------------------------------------------------------===//
 
-void MemOp::build(OpBuilder &builder, OperationState &result,
-                  TypeRange resultTypes, uint32_t readLatency,
-                  uint32_t writeLatency, uint64_t depth, RUWAttr ruw,
-                  ArrayRef<Attribute> portNames, StringRef name,
-                  NameKindEnum nameKind, ArrayRef<Attribute> annotations,
-                  ArrayRef<Attribute> portAnnotations,
-                  hw::InnerSymAttr innerSym) {
-  auto &properties = result.getOrAddProperties<Properties>();
-  properties.setReadLatency(
-      builder.getIntegerAttr(builder.getIntegerType(32), readLatency));
-  properties.setWriteLatency(
-      builder.getIntegerAttr(builder.getIntegerType(32), writeLatency));
-  properties.setDepth(
-      builder.getIntegerAttr(builder.getIntegerType(64), depth));
-  properties.setRuw(::RUWAttrAttr::get(builder.getContext(), ruw));
-  properties.setPortNames(builder.getArrayAttr(portNames));
-  properties.setName(builder.getStringAttr(name));
-  properties.setNameKind(NameKindEnumAttr::get(builder.getContext(), nameKind));
-  properties.setAnnotations(builder.getArrayAttr(annotations));
-  if (innerSym)
-    properties.setInnerSym(innerSym);
-  result.addTypes(resultTypes);
-
-  if (portAnnotations.empty()) {
-    SmallVector<Attribute, 16> portAnnotationsVec(resultTypes.size(),
-                                                  builder.getArrayAttr({}));
-    properties.setPortAnnotations(builder.getArrayAttr(portAnnotationsVec));
-  } else {
-    assert(portAnnotations.size() == resultTypes.size());
-    properties.setPortAnnotations(builder.getArrayAttr(portAnnotations));
-  }
-}
-
-void MemOp::build(OpBuilder &builder, OperationState &result,
-                  TypeRange resultTypes, uint32_t readLatency,
-                  uint32_t writeLatency, uint64_t depth, RUWAttr ruw,
-                  ArrayRef<Attribute> portNames, StringRef name,
-                  NameKindEnum nameKind, ArrayRef<Attribute> annotations,
-                  ArrayRef<Attribute> portAnnotations, StringAttr innerSym) {
-  build(builder, result, resultTypes, readLatency, writeLatency, depth, ruw,
-        portNames, name, nameKind, annotations, portAnnotations,
-        innerSym ? hw::InnerSymAttr::get(innerSym) : hw::InnerSymAttr());
-}
-
 ArrayAttr MemOp::getPortAnnotation(unsigned portIdx) {
   assert(portIdx < getNumResults() &&
          "index should be smaller than result number");