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seldridgeseldridge
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fixup! [FIRRTL] Use new layer ABI
1 parent cff5257 commit 79af01e

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7 files changed

+77
-77
lines changed

7 files changed

+77
-77
lines changed

‎lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ static void appendName(StringRef name, SmallString<32> &output,
6868
return;
6969
if (!output.empty()) {
7070
if (verilogSafe)
71-
output.append("$");
71+
output.append("_");
7272
else
7373
output.append("-");
7474
}
@@ -97,7 +97,7 @@ static SmallString<32> moduleNameForLayer(StringRef moduleName,
9797
}
9898

9999
/// For a layerblock `@A::@B::@C`,
100-
/// the generated instance is called `a$b$c`.
100+
/// the generated instance is called `a_b_c`.
101101
static SmallString<32> instanceNameForLayer(SymbolRefAttr layerName) {
102102
SmallString<32> result;
103103
appendName(layerName, result, /*toLower=*/true, /*verilogSafe=*/true);
@@ -116,7 +116,7 @@ static SmallString<32> fileNameForLayer(StringRef circuitName,
116116
return result;
117117
}
118118

119-
/// For a layerblock `@A::@B::@C`, the verilog macro is `A$B$C`.
119+
/// For a layerblock `@A::@B::@C`, the verilog macro is `A_B_C`.
120120
static SmallString<32>
121121
macroNameForLayer(ArrayRef<FlatSymbolRefAttr> layerName) {
122122
SmallString<32> result;
@@ -864,10 +864,10 @@ void LowerLayersPass::runOnOperation() {
864864
//
865865
// `include "layers-A.sv"
866866
// `include "layers-A-B.sv"
867-
// `ifndef layers$A$B$C
868-
// `define layers$A$B$C
867+
// `ifndef layers_A_B_C
868+
// `define layers_A_B_C
869869
// <body>
870-
// `endif // layers$A$B$C
870+
// `endif // layers_A_B_C
871871
//
872872
// TODO: This would be better handled without the use of verbatim ops.
873873
OpBuilder builder(circuitOp);
@@ -885,18 +885,18 @@ void LowerLayersPass::runOnOperation() {
885885

886886
builder.setInsertionPointToStart(circuitOp.getBodyBlock());
887887

888-
// Save the "layers-<circuit>-<group>" and "layers$<circuit>$<group>" string
888+
// Save the "layers-<circuit>-<group>" and "layers_<circuit>_<group>" string
889889
// as this is reused a bunch.
890-
SmallString<32> prefixFile("layers-"), prefixMacro("layers$");
890+
SmallString<32> prefixFile("layers-"), prefixMacro("layers_");
891891
prefixFile.append(circuitName);
892892
prefixFile.append("-");
893893
prefixMacro.append(circuitName);
894-
prefixMacro.append("$");
894+
prefixMacro.append("_");
895895
for (auto [layer, _] : layers) {
896896
prefixFile.append(layer.getSymName());
897897
prefixFile.append("-");
898898
prefixMacro.append(layer.getSymName());
899-
prefixMacro.append("$");
899+
prefixMacro.append("_");
900900
}
901901
prefixFile.append(layerOp.getSymName());
902902
prefixMacro.append(layerOp.getSymName());

‎test/Dialect/FIRRTL/lower-layers.mlir

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -380,46 +380,46 @@ firrtl.circuit "Test" {
380380

381381
// CHECK: sv.macro.decl @[[INLINE:.*]]["Inline"]
382382
firrtl.layer @Inline inline {
383-
// CHECK: sv.macro.decl @Inline$Inline
383+
// CHECK: sv.macro.decl @Inline_Inline
384384
firrtl.layer @Inline inline {}
385385
firrtl.layer @Bound bind {
386-
// CHECK: sv.macro.decl @Inline$Bound$Inline
386+
// CHECK: sv.macro.decl @Inline_Bound_Inline
387387
firrtl.layer @Inline inline {}
388388
firrtl.layer @Bound bind {
389-
// CHECK: sv.macro.decl @Inline$Bound$Bound$Inline
389+
// CHECK: sv.macro.decl @Inline_Bound_Bound_Inline
390390
firrtl.layer @Inline inline {}
391391
}
392392
}
393393
}
394394

395395
firrtl.layer @Bound bind {
396-
// CHECK: sv.macro.decl @Bound$Inline
396+
// CHECK: sv.macro.decl @Bound_Inline
397397
firrtl.layer @Inline inline {}
398398
}
399399

400-
// CHECK: firrtl.module private @ModuleWithInlineLayerBlocks$Inline$Bound() {
400+
// CHECK: firrtl.module private @ModuleWithInlineLayerBlocks_Inline_Bound() {
401401
// CHECK: %w3 = firrtl.wire : !firrtl.uint<3>
402-
// CHECK: sv.ifdef @Inline$Bound$Inline {
402+
// CHECK: sv.ifdef @Inline_Bound_Inline {
403403
// CHECK: %w4 = firrtl.wire : !firrtl.uint<4>
404404
// CHECK: }
405405
// CHECK: }
406406

407-
// CHECK: firrtl.module private @ModuleWithInlineLayerBlocks$Bound() {
407+
// CHECK: firrtl.module private @ModuleWithInlineLayerBlocks_Bound() {
408408
// CHECK: %w5 = firrtl.wire : !firrtl.uint<5>
409-
// CHECK: sv.ifdef @Bound$Inline {
409+
// CHECK: sv.ifdef @Bound_Inline {
410410
// CHECK: %w6 = firrtl.wire : !firrtl.uint<6>
411411
// CHECK: }
412412
// CHECK: }
413413

414414
// CHECK: firrtl.module @ModuleWithInlineLayerBlocks() {
415415
// CHECK: sv.ifdef @[[INLINE]] {
416416
// CHECK: %w1 = firrtl.wire : !firrtl.uint<1>
417-
// CHECK: sv.ifdef @Inline$Inline {
417+
// CHECK: sv.ifdef @Inline_Inline {
418418
// CHECK: %w2 = firrtl.wire : !firrtl.uint<2>
419419
// CHECK: }
420-
// CHECK: firrtl.instance inline$bound {lowerToBind, output_file = #hw.output_file<"layers-Test-Inline-Bound.sv", excludeFromFileList>} @ModuleWithInlineLayerBlocks$Inline$Bound()
420+
// CHECK: firrtl.instance inline_bound {lowerToBind, output_file = #hw.output_file<"layers-Test-Inline-Bound.sv", excludeFromFileList>} @ModuleWithInlineLayerBlocks_Inline_Bound()
421421
// CHECK: }
422-
// CHECK: firrtl.instance bound {lowerToBind, output_file = #hw.output_file<"layers-Test-Bound.sv", excludeFromFileList>} @ModuleWithInlineLayerBlocks$Bound()
422+
// CHECK: firrtl.instance bound {lowerToBind, output_file = #hw.output_file<"layers-Test-Bound.sv", excludeFromFileList>} @ModuleWithInlineLayerBlocks_Bound()
423423
// CHECK: }
424424
firrtl.module @ModuleWithInlineLayerBlocks() {
425425
firrtl.layerblock @Inline {
@@ -474,38 +474,38 @@ firrtl.circuit "Simple" {
474474
//
475475
// CHECK: sv.verbatim "`include \22layers-Simple-A.sv\22\0A
476476
// CHECK-SAME: `include \22layers-Simple-A-B.sv\22\0A
477-
// CHECK-SAME: `ifndef layers$Simple$A$B$C\0A
478-
// CHECK-SAME: define layers$Simple$A$B$C"
477+
// CHECK-SAME: `ifndef layers_Simple_A_B_C\0A
478+
// CHECK-SAME: define layers_Simple_A_B_C"
479479
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A-B-C.sv", excludeFromFileList>
480480
// CHECK: sv.verbatim "`include \22layers-Simple-A.sv\22\0A
481-
// CHECK-SAME: `ifndef layers$Simple$A$B\0A
482-
// CHECK-SAME: define layers$Simple$A$B"
481+
// CHECK-SAME: `ifndef layers_Simple_A_B\0A
482+
// CHECK-SAME: define layers_Simple_A_B"
483483
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A-B.sv", excludeFromFileList>
484-
// CHECK: sv.verbatim "`ifndef layers$Simple$A\0A
485-
// CHECK-SAME: define layers$Simple$A"
484+
// CHECK: sv.verbatim "`ifndef layers_Simple_A\0A
485+
// CHECK-SAME: define layers_Simple_A"
486486
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A.sv", excludeFromFileList>
487487
//
488-
// CHECK: firrtl.module private @Simple$A$B$C(
488+
// CHECK: firrtl.module private @Simple_A_B_C(
489489
// CHECK-NOT: firrtl.module
490490
// CHECK-SAME: in %[[cc_port:[_a-zA-Z0-9]+]]: !firrtl.uint<3>
491491
// CHECK-NEXT: %ccc = firrtl.node %[[cc_port]]
492492
// CHECK-NEXT: }
493493
//
494-
// CHECK: firrtl.module private @Simple$A$B(
494+
// CHECK: firrtl.module private @Simple_A_B(
495495
// CHECK-NOT: firrtl.module
496496
// CHECK-SAME: in %[[b_port:[_a-zA-Z0-9]+]]: !firrtl.uint<2>
497497
// CHECK-SAME: in %[[c_port:[_a-zA-Z0-9]+]]: !firrtl.uint<3>
498-
// CHECK-SAME: out %[[cc_port:[_a-zA-Z0-9$]+]]: !firrtl.probe<uint<3>>
498+
// CHECK-SAME: out %[[cc_port:[_a-zA-Z0-9_]+]]: !firrtl.probe<uint<3>>
499499
// CHECK-NEXT: %bb = firrtl.node %[[b_port]]
500500
// CHECK-NEXT: %cc = firrtl.node %[[c_port]]
501501
// CHECK-NEXT: %0 = firrtl.ref.send %cc
502502
// CHECK-NEXT: firrtl.ref.define %[[cc_port]], %0
503503
// CHECK-NEXT: }
504504
//
505-
// CHECK: firrtl.module private @Simple$A(
505+
// CHECK: firrtl.module private @Simple_A(
506506
// CHECK-NOT: firrtl.module
507507
// CHECK-SAME: in %[[a_port:[_a-zA-Z0-9]+]]: !firrtl.uint<1>
508-
// CHECK-SAME: out %[[c_port:[_a-zA-Z0-9$]+]]: !firrtl.probe<uint<3>>
508+
// CHECK-SAME: out %[[c_port:[_a-zA-Z0-9_]+]]: !firrtl.probe<uint<3>>
509509
// CHECK-NEXT: %aa = firrtl.node %[[a_port]]
510510
// CHECK: %[[c_ref:[_a-zA-Z0-9]+]] = firrtl.ref.send %c
511511
// CHECK-NEXT: firrtl.ref.define %[[c_port]], %[[c_ref]]
@@ -514,30 +514,30 @@ firrtl.circuit "Simple" {
514514
// CHECK: firrtl.module @Simple() {
515515
// CHECK-NOT: firrtl.module
516516
// CHECK-NOT: firrtl.layerblock
517-
// CHECK: %[[A_B_C_cc:[_a-zA-Z0-9$]+]] = firrtl.instance a$b$c {
517+
// CHECK: %[[A_B_C_cc:[_a-zA-Z0-9_]+]] = firrtl.instance a_b_c {
518518
// CHECK-SAME: lowerToBind
519519
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A-B-C.sv"
520520
// CHECK-SAME: excludeFromFileList
521-
// CHECK-SAME: @Simple$A$B$C(
522-
// CHECK-NEXT: %[[A_B_b:[_a-zA-Z0-9$]+]], %[[A_B_c:[_a-zA-Z0-9$]+]], %[[A_B_cc:[_a-zA-Z0-9$]+]] = firrtl.instance a$b {
521+
// CHECK-SAME: @Simple_A_B_C(
522+
// CHECK-NEXT: %[[A_B_b:[_a-zA-Z0-9_]+]], %[[A_B_c:[_a-zA-Z0-9_]+]], %[[A_B_cc:[_a-zA-Z0-9_]+]] = firrtl.instance a_b {
523523
// CHECK-SAME: lowerToBind
524524
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A-B.sv", excludeFromFileList>
525-
// CHECK-SAME: @Simple$A$B(
525+
// CHECK-SAME: @Simple_A_B(
526526
// CHECK-NEXT: %[[A_B_cc_resolve:[_a-zA-Z0-9]+]] = firrtl.ref.resolve %[[A_B_cc]]
527527
// CHECK-NEXT: firrtl.matchingconnect %[[A_B_C_cc]], %[[A_B_cc_resolve]]
528528
// CHECK-NEXT: firrtl.matchingconnect %[[A_B_b]], %b
529-
// CHECK-NEXT: %[[A_a:[_a-zA-Z0-9$]+]], %[[A_c:[_a-zA-Z0-9$]+]] = firrtl.instance a {
529+
// CHECK-NEXT: %[[A_a:[_a-zA-Z0-9_]+]], %[[A_c:[_a-zA-Z0-9_]+]] = firrtl.instance a {
530530
// CHECK-SAME: lowerToBind
531531
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A.sv", excludeFromFileList>
532-
// CHECK-SAME: @Simple$A(
532+
// CHECK-SAME: @Simple_A(
533533
// CHECK-NEXT: %[[A_c_resolve:[_a-zA-Z0-9]+]] = firrtl.ref.resolve %[[A_c]]
534534
// CHECK-NEXT: firrtl.matchingconnect %[[A_B_c]], %[[A_c_resolve]]
535535
// CHECK-NEXT: firrtl.matchingconnect %[[A_a]], %a
536536
// CHECK: }
537537
//
538-
// CHECK-DAG: sv.verbatim "`endif // layers$Simple$A"
538+
// CHECK-DAG: sv.verbatim "`endif // layers_Simple_A"
539539
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A.sv", excludeFromFileList>
540-
// CHECK-DAG: sv.verbatim "`endif // layers$Simple$A$B"
540+
// CHECK-DAG: sv.verbatim "`endif // layers_Simple_A_B"
541541
// CHECK-SAME: output_file = #hw.output_file<"layers-Simple-A-B.sv", excludeFromFileList>
542542

543543
// -----
@@ -556,7 +556,7 @@ firrtl.circuit "ModuleNameConflict" {
556556

557557
// CHECK-LABEL: firrtl.circuit "ModuleNameConflict"
558558
//
559-
// CHECK: firrtl.module private @[[groupModule:[_a-zA-Z0-9$]+]](in
559+
// CHECK: firrtl.module private @[[groupModule:[_a-zA-Z0-9_]+]](in
560560
//
561561
// CHECK: firrtl.module @ModuleNameConflict()
562562
// CHECK-NOT: firrtl.module
@@ -663,7 +663,7 @@ firrtl.circuit "HierPathOps" {
663663
// CHECK-LABEL: firrtl.circuit "HierPathOps"
664664
//
665665
// CHECK: hw.hierpath @nla1 [@Foo::@foo_A]
666-
// CHECK-NEXT: hw.hierpath @nla2 [@Foo::@[[inst_sym:[_A-Za-z0-9]+]], @[[mod_sym:[_A-Za-z0-9$]+]]::@bar, @Bar]
666+
// CHECK-NEXT: hw.hierpath @nla2 [@Foo::@[[inst_sym:[_A-Za-z0-9]+]], @[[mod_sym:[_A-Za-z0-9_]+]]::@bar, @Bar]
667667
// CHECK-NEXT: hw.hierpath private @nla3 [@Foo::@[[inst_sym]], @[[mod_sym]]::@baz]
668668
//
669669
// CHECK: firrtl.module {{.*}} @[[mod_sym]]()
@@ -710,9 +710,9 @@ firrtl.circuit "Foo" attributes {
710710
// CHECK: sv.verbatim
711711
// CHECK-SAME: #hw.output_file<"testbench{{/|\\\\}}layers-Foo-A.sv", excludeFromFileList>
712712
//
713-
// CHECK: firrtl.module {{.*}} @Bar$A
713+
// CHECK: firrtl.module {{.*}} @Bar_A
714714
// CHECK-SAME: #hw.output_file<"testbench{{/|\\\\}}", excludeFromFileList>
715-
// CHECK: firrtl.module {{.*}} @Foo$A
715+
// CHECK: firrtl.module {{.*}} @Foo_A
716716
// CHECK-SAME: #hw.output_file<"testbench{{/|\\\\}}", excludeFromFileList>
717717
//
718718
// CHECK: sv.verbatim
@@ -731,10 +731,10 @@ firrtl.circuit "Foo" {
731731
}
732732

733733
// CHECK: firrtl.circuit "Foo" {
734-
// CHECK: sv.verbatim "`ifndef layers$Foo$B\0A`define layers$Foo$B" {output_file = #hw.output_file<"layers-Foo-B.sv", excludeFromFileList>}
734+
// CHECK: sv.verbatim "`ifndef layers_Foo_B\0A`define layers_Foo_B" {output_file = #hw.output_file<"layers-Foo-B.sv", excludeFromFileList>}
735735
// CHECK: firrtl.module @Foo() {
736736
// CHECK: }
737-
// CHECK: sv.verbatim "`endif // layers$Foo$B" {output_file = #hw.output_file<"layers-Foo-B.sv", excludeFromFileList>}
737+
// CHECK: sv.verbatim "`endif // layers_Foo_B" {output_file = #hw.output_file<"layers-Foo-B.sv", excludeFromFileList>}
738738
// CHECK: }
739739

740740
// -----
@@ -748,13 +748,13 @@ firrtl.circuit "RWTH" {
748748
%one = firrtl.constant 1 : !firrtl.uint<1>
749749
firrtl.ref.force_initial %one, %d_p, %one: !firrtl.uint<1>, !firrtl.rwprobe<uint<1>, @T>, !firrtl.uint<1>
750750
}
751-
// CHECK: firrtl.module private @DUT$T(out %p: !firrtl.rwprobe<uint<1>>) {
751+
// CHECK: firrtl.module private @DUT_T(out %p: !firrtl.rwprobe<uint<1>>) {
752752
// CHECK-NEXT: %w = firrtl.wire sym @[[SYM:.+]] : !firrtl.uint<1>
753-
// CHECK-NEXT: %0 = firrtl.ref.rwprobe <@DUT$T::@[[SYM]]> : !firrtl.rwprobe<uint<1>>
753+
// CHECK-NEXT: %0 = firrtl.ref.rwprobe <@DUT_T::@[[SYM]]> : !firrtl.rwprobe<uint<1>>
754754
// CHECK-NEXT: firrtl.ref.define %p, %0 : !firrtl.rwprobe<uint<1>>
755755
// CHECK-NEXT: }
756756
// CHECK-NEXT: firrtl.module @DUT(out %p: !firrtl.rwprobe<uint<1>>) attributes {convention = #firrtl<convention scalarized>} {
757-
// CHECK-NEXT: %t_p = firrtl.instance t sym @t {lowerToBind, output_file = #hw.output_file<"layers-RWTH-T.sv", excludeFromFileList>} @DUT$T(out p: !firrtl.rwprobe<uint<1>>)
757+
// CHECK-NEXT: %t_p = firrtl.instance t sym @t {lowerToBind, output_file = #hw.output_file<"layers-RWTH-T.sv", excludeFromFileList>} @DUT_T(out p: !firrtl.rwprobe<uint<1>>)
758758
// CHECK-NEXT: firrtl.ref.define %p, %t_p : !firrtl.rwprobe<uint<1>>
759759
// CHECK-NEXT: }
760760

‎test/firtool/layers-rwprobe.fir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ FIRRTL version 4.0.0
1515
; CHECK-NEXT: DUT d ();
1616
; CHECK-NEXT: endmodule
1717

18-
; CHECK: module DUT$T();
18+
; CHECK: module DUT_T();
1919
; CHECK-NEXT: wire w = 1'h0;
2020
; CHECK-NEXT: endmodule
2121
;

‎test/firtool/layers.fir

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ circuit Foo: %[[
3737
node z = x
3838
assert(clock, cond, enable, "Test")
3939

40-
; CHECK-LABEL: module Foo$A$B(
40+
; CHECK-LABEL: module Foo_A_B(
4141
; CHECK-NEXT: input x,
4242
; CHECK-NEXT: cond,
4343
; CHECK-NEXT: enable,
@@ -51,28 +51,28 @@ circuit Foo: %[[
5151
; CHECK-NEXT: end // always @(posedge)
5252
; CHECK-NEXT: endmodule
5353

54-
; CHECK-LABEL: module Foo$A(
54+
; CHECK-LABEL: module Foo_A(
5555
; CHECK-NEXT: input in
5656
; CHECK: wire x = in;
5757
; CHECK-NEXT: wire x_probe = x;
5858
; CHECK-NEXT: endmodule
5959

6060
; CHECK-LABEL: FILE "layers-Foo-A-B.sv"
6161
; CHECK: `include "layers-Foo-A.sv"
62-
; CHECK-NEXT: `ifndef layers$Foo$A$B
63-
; CHECK-NEXT: `define layers$Foo$A$B
64-
; CHECK-NEXT: bind Foo Foo$A$B a$b (
62+
; CHECK-NEXT: `ifndef layers_Foo_A_B
63+
; CHECK-NEXT: `define layers_Foo_A_B
64+
; CHECK-NEXT: bind Foo Foo_A_B a_b (
6565
; CHECK-NEXT: .x (Foo.a.x_probe),
6666
; CHECK-NEXT: .cond (cond),
6767
; CHECK-NEXT: .enable (enable),
6868
; CHECK-NEXT: .clock (clock)
6969
; CHECK-NEXT: );
70-
; CHECK-NEXT: `endif // layers$Foo$A$B
70+
; CHECK-NEXT: `endif // layers_Foo_A_B
7171

7272
; CHECK-LABEL: FILE "layers-Foo-A.sv"
73-
; CHECK: `ifndef layers$Foo$A
74-
; CHECK-NEXT: `define layers$Foo$A
75-
; CHECK-NEXT: bind Foo Foo$A a (
73+
; CHECK: `ifndef layers_Foo_A
74+
; CHECK-NEXT: `define layers_Foo_A
75+
; CHECK-NEXT: bind Foo Foo_A a (
7676
; CHECK-NEXT: .in (in)
7777
; CHECK-NEXT: );
78-
; CHECK-NEXT: `endif // layers$Foo$A
78+
; CHECK-NEXT: `endif // layers_Foo_A

‎test/firtool/lower-layers-directories.fir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ circuit Testbench: %[[
3232
"component": []
3333
},
3434
"tpe": {
35-
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
35+
"class": "sifive.enterprise.grandcentral.GrandCentralView_UnknownGroundType_"
3636
}
3737
}
3838
}
@@ -120,7 +120,7 @@ circuit Testbench: %[[
120120
;
121121
; CHECK-DAG: FILE "verification{{[/\]}}testbench{{[/\]}}layers-Testbench-A.sv"
122122
; CHECK-DAG: FILE "verification{{[/\]}}testbench{{[/\]}}Bar.sv"
123-
; CHECK-DAG: FILE "verification{{[/\]}}testbench{{[/\]}}DUT$A.sv"
123+
; CHECK-DAG: FILE "verification{{[/\]}}testbench{{[/\]}}DUT_A.sv"
124124
; CHECK-DAG: FILE "verification{{[/\]}}testbench{{[/\]}}Testbench.sv"
125125

126126
; The following modules are all in the Grand Central directory.

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