[ESI] Getting ESI primitives run in iverilog

Modify both the primitive file itself and the testbench to run in Icarus
Verilog. Also, pull the location into lit via a substitution.

Author: teqdruid

integration_test/CMakeLists.txt

@@ -46,6 +46,9 @@ if (ESI_RUNTIME)
   endif()
 endif()
 
+get_target_property(ESI_PrimsDir ESIPrimitives SOURCE_DIR)
+set(ESI_Prims "${ESI_PrimsDir}/ESIPrimitives.sv")
+
 set(CIRCT_INTEGRATION_TIMEOUT 60) # Set a 60s timeout on individual tests.
 configure_lit_site_cfg(
   ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.py.in

integration_test/Dialect/ESI/primitives/primitive_tb.sv

@@ -1,6 +1,5 @@
 // REQUIRES: ieee-sim
-// UNSUPPORTED: ieee-sim-iverilog
-// RUN: circt-rtl-sim.py --sim %ieee-sim %CIRCT_SOURCE%/lib/Dialect/ESI/ESIPrimitives.sv %s
+// RUN: circt-rtl-sim.py --sim %ieee-sim %esi_prims %s
 
 //===- primitive_tb.sv - tests for ESI primitives -----------*- verilog -*-===//
 //
@@ -10,6 +9,10 @@
 //
 //===----------------------------------------------------------------------===//
 
+`define assert_fatal(pred) \
+  if (!(pred)) \
+    $fatal();
+
 module top (
   input logic clk,
   input logic rst
@@ -25,13 +28,21 @@ module top (
 
 
   ESI_PipelineStage s1 (
-      .*
+    .clk(clk),
+    .rst(rst),
+    .a_valid(a_valid),
+    .a(a),
+    .a_ready(a_ready),
+    .x_valid(x_valid),
+    .x(x),
+    .x_ready(x_ready)
   );
 
   // Increment the input every cycle.
   always begin
     @(posedge clk) #1;
-    a++;
+    if (~rst)
+      a++;
   end
 
   // Track the number of tokens currently in the stage for debugging.
@@ -44,98 +55,97 @@ module top (
   end
 
   initial begin
-    // Wait until rstn is deasserted.
-    while (rst) begin
-      @(posedge clk);
-    end
+    // Wait until rst is deasserted.
+    @(negedge rst);
+    @(posedge clk);
 
     a_valid = 1;
-    assert (a_ready);
+    `assert_fatal (a_ready);
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h05);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h02);
+    `assert_fatal (a_ready);
 
     a_valid = 1;
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h05);
-    assert (~a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h02);
+    `assert_fatal (~a_ready);
     a_valid = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h05);
-    assert (~a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h02);
+    `assert_fatal (~a_ready);
     x_ready = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h06);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h03);
+    `assert_fatal (a_ready);
     x_ready = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h09);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h06);
+    `assert_fatal (a_ready);
     x_ready = 0;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h09);
-    assert (~a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h06);
+    `assert_fatal (~a_ready);
     x_ready = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h0A);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h07);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 0;
 
     @(posedge clk) #1;
-    assert (~x_valid);
-    assert (a_ready);
+    `assert_fatal (~x_valid);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 0;
 
     @(posedge clk) #1;
-    assert (~x_valid);
-    assert (a_ready);
+    `assert_fatal (~x_valid);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 0;
 
     @(posedge clk) #1;
-    assert (~x_valid);
-    assert (a_ready);
+    `assert_fatal (~x_valid);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 0;
 
     @(posedge clk) #1;
-    assert (~x_valid);
-    assert (a_ready);
+    `assert_fatal (~x_valid);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h10);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h0D);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h11);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h0E);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 1;
 
     @(posedge clk) #1;
-    assert (x_valid);
-    assert (x == 8'h12);
-    assert (a_ready);
+    `assert_fatal (x_valid);
+    `assert_fatal (x == 8'h0F);
+    `assert_fatal (a_ready);
     x_ready = 1;
     a_valid = 1;
 
@@ -145,7 +155,7 @@ module top (
     @(posedge clk) #1;
     @(posedge clk) #1;
     @(posedge clk) #1;
-    $stop();
+    $finish();
   end
 
 endmodule

integration_test/lit.cfg.py

@@ -169,6 +169,8 @@
 if ieee_sims and ieee_sims[-1][1] == config.iverilog_path:
   config.available_features.add('ieee-sim-iverilog')
 
+config.substitutions.append(("%esi_prims", config.esi_prims))
+
 # Enable ESI runtime tests.
 if config.esi_runtime == "1":
   config.available_features.add('esi-runtime')

integration_test/lit.site.cfg.py.in

@@ -50,6 +50,7 @@ config.clang_tidy_path = "@CLANG_TIDY_PATH@"
 config.have_systemc = "@HAVE_SYSTEMC@"
 config.esi_runtime = "@ESI_RUNTIME@"
 config.esi_runtime_path = "@ESIRuntimePath@"
+config.esi_prims = "@ESI_Prims@"
 config.bindings_python_enabled = @CIRCT_BINDINGS_PYTHON_ENABLED@
 config.bindings_tcl_enabled = @CIRCT_BINDINGS_TCL_ENABLED@
 config.lec_enabled = "@CIRCT_LEC_ENABLED@"

lib/Dialect/ESI/ESIPrimitives.sv

@@ -36,7 +36,7 @@
 /// | --- | ----- | --------- | ------- | ------ | ------------------ |
 ///
 module ESI_PipelineStage # (
-  int WIDTH = 8
+  parameter WIDTH = 8
 ) (
   input logic clk,
   input logic rst,
@@ -80,7 +80,7 @@ module ESI_PipelineStage # (
   // Did we accept a token this cycle?
   wire a_rcv = a_ready && a_valid;
 
-  always_ff @(posedge clk) begin
+  always @(posedge clk) begin
     if (rst) begin
       l_valid <= 1'b0;
       x_valid_reg <= 1'b0;

tools/circt-rtl-sim/circt-rtl-sim.py.in

@@ -326,7 +326,7 @@ def __main__(args):
   if not args.no_compile:
     rc = sim.compile(args.sources, args.compileargs)
     if rc.returncode != 0:
-      return rc
+      return rc.returncode
   if not args.no_run:
     try:
       rc = sim.run(args.cycles, args.simargs)